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DTSTAMP:20240626T180034Z
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DTSTART;TZID=America/Los_Angeles:20240626T180000
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UID:dac_DAC 2024_sess256_LBR116@linklings.com
SUMMARY:Late Breaking Results: Majority-Inverter Graph Minimization by Des
 ign Space Exploration
DESCRIPTION:Late Breaking Results Poster\n\nSiang-Yun Lee and Alessandro T
 empia Calvino (École Polytechnique Fédérale de Lausanne); Heinz Riener (Ca
 dence Design Systems, Inc.); and Giovanni De Micheli (École Polytechnique 
 Fédérale de Lausanne)\n\nThe majority-inverter graph (MIG) is a homogeneou
 s logic network widely used in logic synthesis for majority-based emerging
  technologies. Many logic optimization algorithms have been proposed for M
 IGs, including rewriting, resubstitution, and graph mapping. However, unli
 ke AIGs, research on optimization flows for MIGs is limited. In this paper
 , we explore combinations of well-developed MIG optimization algorithms us
 ing an on-the-fly design space exploration strategy and present the latest
  best results on MIG size minimization of EPFL benchmarks. Significant red
 uctions (of 88% and 79%) are observed for two specific benchmarks and an a
 verage of 14% improvement is achieved compared to the state-of-the-art flo
 w.
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