Presentation
Hardware Security at RTL - an AI/ML-based Approach
DescriptionMicroelectronics are essential to critical infrastructure, yet they are increasingly at risk from cyber attacks and malicious hardware modifications. The current state of security analysis primarily addresses known threats, leaving undiscovered vulnerabilities largely concealed on the dark side of the attack surface.
We will introduce a patented Register Transfer Level (RTL) analysis technique that offers both qualitative and quantitative insights into semiconductor designs. This advanced methodology identifies and quantifies potential vulnerabilities that are susceptible to attack vectors that target functional behavior, operational reliability, and data integrity.
This predictive approach facilitates the cyber hardening of designs and helps achieve convergence on device-level security coverage. Furthermore, our experimental results show that the framework can be used to detect in-field attack. We utilize machine learning to adaptively recognize threats, and can demonstrate on-chip integration of next-generation protection into the semiconductor design lifecycle.
This session will detail our innovative approach, emphasize the importance of proactive security measures in the design phase of microelectronics development, and how this platform can reveal, surveil, quarantine, and remediate sophisticated cyber threats to improve the cyber resilience of critical electronic systems.
We will introduce a patented Register Transfer Level (RTL) analysis technique that offers both qualitative and quantitative insights into semiconductor designs. This advanced methodology identifies and quantifies potential vulnerabilities that are susceptible to attack vectors that target functional behavior, operational reliability, and data integrity.
This predictive approach facilitates the cyber hardening of designs and helps achieve convergence on device-level security coverage. Furthermore, our experimental results show that the framework can be used to detect in-field attack. We utilize machine learning to adaptively recognize threats, and can demonstrate on-chip integration of next-generation protection into the semiconductor design lifecycle.
This session will detail our innovative approach, emphasize the importance of proactive security measures in the design phase of microelectronics development, and how this platform can reveal, surveil, quarantine, and remediate sophisticated cyber threats to improve the cyber resilience of critical electronic systems.
Event Type
Exhibitor Forum
TimeMonday, June 244:15pm - 4:45pm PDT
LocationExhibitor Forum, Level 1 Exhibit Hall