Contributors
A
Work-in-Progress Poster PCBench: A Dataset for Printed Circuit Board Routing
Work-in-Progress Poster An Open-Source Framework for AMS Modeling and Verification
Research Manuscript Bitwise Adaptive Early Termination in Hyperdimensional Computing Inference
Work-in-Progress Poster Evergreen: Comprehensive Carbon Modeling for Performance-Emission Tradeoffs
Engineering Track Poster Pnr implementation challenges in 3d ic
Engineering Track Poster Avoiding CDC bugs introduced during Synthesis Optimizations and Netlist Transformations
Research Manuscript Levioso: Efficient Compiler-Informed Secure Speculation
Engineering Track Poster Quality Assurance of DRC deck for Devices by SKILL Automation
Engineering Track Poster Calibre Autowaiver for Early DRC & DFM Analysis In Big Die Designs
Research Manuscript SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks
Work-in-Progress Poster Solving Maximum Flows of Undirected Graphs by Minimizing s-t Effective Resistances of Electrical Networks
Work-in-Progress Poster Stability Analysis of Integrated Circuits via Graph Neural Networks
Research Manuscript DGR: Differentiable Global Router
Back-End Design A Systematic Approach to 3D Cutline Exploration and Benchmarking
Research Manuscript Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS
Late Breaking Results Poster Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Work-in-Progress Poster Retract: Logarithmic-Depth Reconstruction of Continuous Controlled-NOT Logic Block
Back-End Design Model Margining Algorithm for High Performance SOC closure
Work-in-Progress Poster Knowledge is Power: A Knowledge-Guided Oracle-Less Attack on Logic Locking
Work-in-Progress Poster VisionHD: Revisiting Hyperdimensional Computing for Improved Image Classification
Engineering Track Poster New SoC Creation Flow based on Extraction and recreating from previous SoC
Engineering Track Poster A Novel approach to implement FuSA Feature in Complex Automotive SoCs Using USF
Work-in-Progress Poster TDM: Time and Distance based Metric for Quantifying Information Leakage Vulnerabilities in SoCs
Work-in-Progress Poster Pre-Silicon Power Side-channel Leakage Assessment of CRYSTALS-Kyber
Engineering Track Poster High Coverage QA for Process Variability Compensation in LVS Rule Deck
Engineering Track Poster Coverage-based FV signoff – The complete cleanup methodology
Work-in-Progress Poster Distributed Inference of DL Workloads on CIM-based Heterogeneous Accelerators
Research Manuscript LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
Late Breaking Results Poster Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Work-in-Progress Poster Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era
Work-in-Progress Poster Additive Partial Sum Quantization
Work-in-Progress Poster PIANIST: Efficient Quantum Circuit Simulation using Commercial Processing-in-Memory System
Front-End Design Static and Formal Verification: Pillars of Modern Design Assurance
Engineering Track Poster Peak Power Optimization using Active Datapath Operator Profiling
Research Manuscript ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours
Research Manuscript Heterogeneous and Reconfigurable Architecture: Applications and Tools
Research Manuscript CLUMAP: Clustered Mapper for CGRAs with Predication
Work-in-Progress Poster Confidential Computing with Heterogeneous Devices at Cloud-Scale
Work-in-Progress Poster Principles for Enabling TEEs on Domain-Specific Accelerators
Research Manuscript DNN-Defender: A Victim-Focused In-DRAM Defense Mechanism for Taming Adversarial Weight Attack on DNNs
Work-in-Progress Poster Enhancing Edge Computing with In/Near-Sensor Processing Schemes for Vision Transformers
Research Manuscript HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI
Engineering Track Poster Advancements in Source Synchronous Design Implementation: An EDA Perspective
Engineering Track Poster Balancing Power and Performance: The Hybrid Clock Network Approach for Network on chips
Engineering Track Poster Peak Power Optimization using Active Datapath Operator Profiling
Research Manuscript LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
Late Breaking Results Poster Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Late Breaking Results Poster Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas
Research Manuscript Advanced Reinforcement Learning Algorithms to Optimize Design Verification
Research Manuscript Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip
Research Manuscript GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
Engineering Track Poster Charting Uncharted Waters: Functional Simulation Reshaping CDC/RDC Constraints Signoff
Embedded Systems and Software Edge Intelligence & GenAI: Exploring Challenges and Ethics
Work-in-Progress Poster VisionHD: Revisiting Hyperdimensional Computing for Improved Image Classification
Engineering Track Poster Challenges and Improvements in StandardCell OpenAccess Content for Analog Design
Engineering Track Poster Integrated Calculation of Capacitances for Image Sensor Arrays and other Periodic Designs
Work-in-Progress Poster TDM: Time and Distance based Metric for Quantifying Information Leakage Vulnerabilities in SoCs
B
Research Manuscript RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Engineering Track Poster A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Engineering Track Poster Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Research Manuscript VVIP: Versatile Vertical Indexing Processor for Edge Computing
Special Session (Research) Invited: Using Causal Information to Enable More Efficient Robot Operation
Research Manuscript ChatPattern: Layout Pattern Customization via Natural Language
Research Manuscript Unleashing the Power of T1-cells in SFQ Arithmetic Circuits
Engineering Track Poster Future Proofing Chiplet Testbenches: Resilience in Multiprotocol Era
Work-in-Progress Poster Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators
Exhibitor Forum Object Oriented Embedded Hardware for Operational Excellence
Engineering Track Poster Early detection of low power related issues using formal verification
Engineering Track Poster Dashboard Model for Foundry Early Node Assessments using Synopsys Design.da
Engineering Track Poster Automated Place and Route based solution for Custom Blocks
Engineering Track Poster Matched Placement and Routing using Synchronized Unit Cell Array
Engineering Track Poster Avoiding CDC bugs introduced during Synthesis Optimizations and Netlist Transformations
Work-in-Progress Poster PCBench: A Dataset for Printed Circuit Board Routing
China
Research Manuscript Net Resource Allocation: A Desirable Initial Routing Step
Research Manuscript PathFuzz: Broadening Fuzzing Horizons with Footprint Memory for CPUs
Engineering Track Poster Memory Clusters – Divide the design and optimize MBIST insertion efforts
Work-in-Progress Poster A Hardware-Aware Framework for Practical Quantum Circuit Knitting
Work-in-Progress Poster A Quantum Solver for the Boolean Matching Problem
Research Manuscript Design of a Quantum Walk Circuit to Solve the Subset-Sum Problem
Engineering Track Poster Avoiding CDC bugs introduced during Synthesis Optimizations and Netlist Transformations
Work-in-Progress Poster A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Research Manuscript DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications
Research Manuscript Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems
Research Manuscript MENDNet: Just-in-time Fault Detection and Mitigation in AI Systems with Uncertainty Quantification and Multi-Exit Networks
Research Manuscript NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance
Research Manuscript Quantum Real Problem Solver
Engineering Track Poster Executable Tables, 'A Journey from Document to Simulation Capable, Exemplified Using DDR5 '
Work-in-Progress Poster Compression with Attention: Learning in Lower Dimensions
Work-in-Progress Poster Zero-Space Cost Fault Tolerance for Transformer-based language models on ReRAM
Research Manuscript Duet: A Collaborative User Driven Recommendation System for Edge Devices
Work-in-Progress Poster Evergreen: Comprehensive Carbon Modeling for Performance-Emission Tradeoffs
Research Manuscript GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
Work-in-Progress Poster Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)
Engineering Track Poster Quality Assurance of DRC deck for Devices by SKILL Automation
Engineering Track Poster Automated Place and Route based solution for Custom Blocks
Engineering Track Poster Resolving the seed promotion due to device layers derivation
Engineering Track Poster Empowering CDC analysis methodology with root cause analysis
Engineering Track Poster An effective Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs
Research Manuscript PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference
Engineering Track Poster True-Hybrid SaaS Cloud Architectures for EDA Workloads
Engineering Track Poster Auto Grouping And Improvement Of IR Critical Regions Using Unsupervised Learning
Work-in-Progress Poster Deputy NoC: A Case of Low Cost Network-on-Chip for Neural Network Accelerations on GPUs
Engineering Track Poster Design Enablement of 2D/3D Power-Thermal Self-Consistent Analysis
Work-in-Progress Poster A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Late Breaking Results Poster Late Breaking Results: A real-time diffusion-based filter for human pose estimation on edge devices
Engineering Track Poster Enhancing and accelerating Verification with ad-hoc Python scripting
Work-in-Progress Poster GPU-Accelerated BFS for Dynamic Networks
Late Breaking Results Poster Late Breaking Results: A real-time diffusion-based filter for human pose estimation on edge devices
Research Manuscript NOFIS: Normalizing Flow for Rare Circuit Failure Analysis
Embedded Systems and Software Edge Intelligence & GenAI: Exploring Challenges and Ethics
Back-End Design Design Automation Advancement in the Analog Domain
Work-in-Progress Poster Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era
Late Breaking Results Poster Late Breaking Results: On the One-Key Premise of Logic Locking
Work-in-Progress Poster Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era
Late Breaking Results Poster Late Breaking Results: A real-time diffusion-based filter for human pose estimation on edge devices
Work-in-Progress Poster Enhancing Delay-driven LUT Mapping with Boolean Decomposition
Work-in-Progress Poster Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators
Work-in-Progress Poster Accelerating DNN Execution via Weight and Data Adaptive N:M Pruning
DAC Pavilion Panel A New Design Verification Era as Open-Source Upends the Status Quo
Work-in-Progress Poster Multi-modal Signal applied Dynamic neuron based Spike processor for Stress Detection
Work-in-Progress Poster Multi-modal Signal applied Neuromorphic proven SNN Model for Stress Detection
Research Manuscript Analog Design Verification and Layout Synthesis Rethought
Work-in-Progress Poster GPU-Accelerated BFS for Dynamic Networks
Work-in-Progress Poster Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era
Work-in-Progress Poster Don't Cache, Speculate!: Speculative Address Translation for Flash-based Storage Systems
Engineering Track Poster Machine Learning Optimization Switch cells.
C
Engineering Track Poster Developing Software Test Library (STL) as a Safety Mechanism for Vision AI DSP
Research Manuscript Net Resource Allocation: A Desirable Initial Routing Step
Work-in-Progress Poster ATAFAN: Design-Friendly Aging-aware Timing Analysis Framework Based on Hybrid Graph Network
Late Breaking Results Poster Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion
Late Breaking Results Poster Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards
Work-in-Progress Poster MatHE: A Near-Mat Processing In-Memory Accelerator for Fully Homomorphic Encryption
Work-in-Progress Poster Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators
Research Manuscript FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA
Research Manuscript FNM-Trans: Efficient FPGA-based Transformer Architecture with Full N:M Sparsity
Work-in-Progress Poster A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
Research Manuscript Analog Design Verification and Layout Synthesis Rethought
Work-in-Progress Poster Adaptive Graph Learning for Efficient Thermal Analysis of the Chiplet System under Interface Variations
Work-in-Progress Poster Addressing the Diversity in AI Computing: An On-chip Programmable Accelerator
Work-in-Progress Poster Analytical Modeling and Electro-Thermal Benchmarking of 2.5D/3D Heterogeneous Integration for AI Computing
Work-in-Progress Poster Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories
Research Manuscript Where Analog, Digital, and ML/AI Meet!
Work-in-Progress Poster Confidential Computing with Heterogeneous Devices at Cloud-Scale
Work-in-Progress Poster Principles for Enabling TEEs on Domain-Specific Accelerators
Research Manuscript MTL-Split: Multi-Task Learning for Edge Devices using Split Computing
Research Manuscript "Memory Is the Scribe of the Soul" Be It Volatile or Not
Research Manuscript ALVEARE: a Domain-Specific Framework for Regular Expressions
Research Manuscript Conjuring: Leaking Control Flow via Speculative Fetch Attacks*
Research Manuscript Levioso: Efficient Compiler-Informed Secure Speculation
Work-in-Progress Poster Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
Research Manuscript Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue
Work-in-Progress Poster A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Research Manuscript SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs
Research Manuscript CircuitVAE: Efficient and Scalable Latent Circuit Optimization
Research Manuscript GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
Special Session (Research) Revolutionizing Edge Autonomy with Cognitive Multispectral Sensing
Work-in-Progress Poster TinySeg: Memory-efficient Image Segmentation for Small Embedded Systems
Research Manuscript Uncovering Software-Based Power Side-Channel Attacks on Apple M1/M2 Systems
Research Manuscript MTL-Split: Multi-Task Learning for Edge Devices using Split Computing
Research Manuscript MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing
Work-in-Progress Poster Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)
Engineering Track Poster Solving Memory Subsystem Verification Challenges for Multi-Instance Designs
Exhibitor Forum Object Oriented Embedded Hardware for Operational Excellence
Research Manuscript Learn and Fuzz!
Back-End Design A Systematic Approach to 3D Cutline Exploration and Benchmarking
Research Manuscript G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis
Research Manuscript Ink: Efficient Incremental k-Critical Path Generation
Work-in-Progress Poster DNNPhaser: Enhancing Data Locality Using Multiphase Ring Dataflow for Spatial Accelerators
Research Manuscript G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis
Back-End Design Design Automation Advancement in the Analog Domain
Research Manuscript CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis
Work-in-Progress Poster A Fast IR-drop Modeling for In-RRAM Computing Considering Data Allocation
Special Session (Research) Invited: Physical Design for Heterogeneous Integration: Challenges and Solutions
Late Breaking Results Poster Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints
Late Breaking Results Poster Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards
Research Manuscript Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes
Work-in-Progress Poster CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell Reprogramming
Research Manuscript How to Steal CPU Idle Time When Synchronous I/O Mode Becomes Promising
Engineering Track Poster SigmaDVD: High Coverage Solution for Power Integrity Signoff
Work-in-Progress Poster Eliminate control divergence in SpMV via in-SRAM reduction
Work-in-Progress Poster Representation-Independent Resubstitution for Area-Oriented Logic Optimization
Work-in-Progress Poster Optimal Toffoli-Depth Quantum Adder
Research Manuscript Defending against Adversarial Patches using Dimensionality Reduction
Research Manuscript Uncovering Software-Based Power Side-Channel Attacks on Apple M1/M2 Systems
Research Manuscript Fast Virtual Gate Extraction For Silicon Quantum Dot Devices
Research Manuscript Sharry：An Efficient and Sharing Far Memory System
Research Manuscript Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection
Special Session (Research) Invited: New Solutions on LLM Acceleration, Optimization, and Application
Research Manuscript Fix Quantum Errors to Win BQSKits
Late Breaking Results Poster Late Breaking Results: Extracting QNNs from NISQ Computers via Ensemble Learning
Research Manuscript TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer*
Research Manuscript Efficient Bilevel Source Mask Optimization
Research Manuscript Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer
Work-in-Progress Poster ATAFAN: Design-Friendly Aging-aware Timing Analysis Framework Based on Hybrid Graph Network
Research Manuscript Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA
Work-in-Progress Poster CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell Reprogramming
Late Breaking Results Poster Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion
Late Breaking Results Poster Mixed-Cell-Height Detailed Placement under Multi-Cell Spacing Constraints
Work-in-Progress Poster Circuit Transformer: End-to-end Logic Synthesis by Predicting the Next Gate
Work-in-Progress Poster ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript Deep Reorganization: Retaining Residuals in TinyML
Late Breaking Results Poster Late Breaking Result: AQFP-aware Binary Neural Network Architecture Search
Back-End Design A Systematic Approach to 3D Cutline Exploration and Benchmarking
Work-in-Progress Poster A Multi-objective Optimization Framework of Spiking Neural Network and Neuromorphic Processor
Work-in-Progress Poster From RTL to Prompt: AN LLM-assisted Verification Methodology for General Processor
Research Manuscript Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes
Work-in-Progress Poster Defending Membership Inference Attack on Edge using Trusted Execution Environments
Research Manuscript Boolean Matching Reversible Circuits: Algorithm and Complexity
Research Manuscript AccMoS: Accelerating Model Simulation for Simulink via Code Generation
Research Manuscript Older and Wise: The Marriage of Device Aging and Intellectual Property Protection of DNNs
Research Manuscript ReCG: ReRAM-Accelerated Sparse Conjugate Gradient
Research Manuscript Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes
Work-in-Progress Poster CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell Reprogramming
Late Breaking Results Poster Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion
Research Manuscript Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning
Research Manuscript ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model
Work-in-Progress Poster CIM for LLM: A Compute-In-Memory Architecture for Efficient Large Language Model Inference
Research Manuscript SPeeDY: Innovative Strategies for Synthesis, Placement, DRC, and Yield
Research Manuscript LLM-HD: Layout Language Model for Hotspot Detection with GDS Semantic Encoding*
Research Manuscript A High-Throughput Private Inference Engine Based on 3D Stacked Memory
Research Manuscript RISC-V Instruction Set Extensions for Multi-Precision Integer Arithmetic
Research Manuscript Combining Parameterized Pulses and Contextual Subspace for More Practical VQE
Work-in-Progress Poster QPulse: Ansatz Design Analysis and Advantages of Parameterized Quantum Pulses
Work-in-Progress Poster RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
Research Manuscript Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip
Work-in-Progress Poster Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction
Research Manuscript Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
Work-in-Progress Poster AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator using Adaptive Posit and Speculative Alignment
Work-in-Progress Poster Additive Partial Sum Quantization
Research Manuscript Genetic Quantization-Aware Approximation for Non-Linear Operations in Transformers
Research Manuscript SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks
Work-in-Progress Poster Stability Analysis of Integrated Circuits via Graph Neural Networks
Research Manuscript AccMoS: Accelerating Model Simulation for Simulink via Code Generation
Research Manuscript MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction
Late Breaking Results Poster Late Breaking Results: On the One-Key Premise of Logic Locking
Research Manuscript Uncovering Software-Based Power Side-Channel Attacks on Apple M1/M2 Systems
Work-in-Progress Poster Adaptive Graph Learning for Efficient Thermal Analysis of the Chiplet System under Interface Variations
Work-in-Progress Poster Analytical Modeling and Electro-Thermal Benchmarking of 2.5D/3D Heterogeneous Integration for AI Computing
Research Panel Generative AI for Chip Design: Game Changer or Damp Squib?
Research Manuscript GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
Research Manuscript SPeeDY: Innovative Strategies for Synthesis, Placement, DRC, and Yield
Research Manuscript Laser Shield: a Physical Defense with Polarizer against Laser Attack
Research Manuscript HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks
Engineering Track Poster Auto Grouping And Improvement Of IR Critical Regions Using Unsupervised Learning
Engineering Track Poster Calibre Autowaiver for Early DRC & DFM Analysis In Big Die Designs
Engineering Track Poster Holistic Approach on 3DIC Planning
Research Manuscript G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis
Front-End Design Systematic Flow on AC Scan Timing/ATPG Constraint Generation
Engineering Track Poster Systematic Flow on AC Scan Timing/ATPG Constraint Generation
Research Manuscript MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
Back-End Design ML based PPA Push using DRV Prediction
Research Manuscript MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
Work-in-Progress Poster Worst Case Response Time Analysis for Completely Fair Scheduling in Linux Systems
Engineering Track Poster Design Methodologies for Minimizing Local Routing Congestions in Low-level Metal Layers
Research Manuscript Nona: Accurate Power Prediction Model Using Neural Networks
Engineering Track Poster A Data-Driven Automation Method of Liberty Model Characterization for Custom Cells
Research Manuscript ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Back-End Design Memory IO Block Routing Optimization using Semi-Automation of Single Trunk Steiner Tree Routing
Engineering Track Poster Methodology of linking the LDR and DRC code by automatically generated test pattern
Engineering Track Poster Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Engineering Track Poster Unified Waveform Analysis Platform for Tr.-Level Design Verification
Research Manuscript MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
Work-in-Progress Poster PIANIST: Efficient Quantum Circuit Simulation using Commercial Processing-in-Memory System
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Work-in-Progress Poster Optimization of DSP-Based Equalizer in High-Speed ADC-Based Receivers
Work-in-Progress Poster Optimizing Homomorphic Convolution for Private CNN Inference
Work-in-Progress Poster RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
Embedded Systems and Software Complex application mapping to heterogeneous compute resources
Work-in-Progress Poster A General Purpose IMC Architecture with ADC-Awared Neural Networks
Research Manuscript GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions
Research Manuscript AI Paradigms beyond Deep Neural Networks
Engineering Track Poster Advanced Static Methodology for Complete Connectivity and Glitch Signoff
Research Manuscript TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer*
Back-End Design A Systematic Approach to 3D Cutline Exploration and Benchmarking
Research Manuscript MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof
Work-in-Progress Poster High-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory Region
Research Manuscript LIVAK: A High-Performance In-Memory Learned Index for Variable-Length Keys
Engineering Track Poster Automated Constraint Promotion Methodology from IP to SoC for Complex Designs
Research Manuscript Predicting Lemmas in Generalization of IC3
Research Manuscript Symbolic Quick Error Detection by Semantically Equivalent Program Execution
Research Manuscript RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Research Manuscript Advanced in Silicon Lifecycle Management & Test
DAC Pavilion Panel Advancing Chip Security to Meet Heightened Requirements
Research Manuscript ALVEARE: a Domain-Specific Framework for Regular Expressions
Research Manuscript Field Programmable Quantum Array Compilation with Flying Ancillas
Research Manuscript SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering
Engineering Track Poster Predicting Computer Resource Needs using Machine Learning and Conventional Design
Work-in-Progress Poster AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs
Work-in-Progress Poster Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Special Session (Research) Invited: Achieving PetaOps/W Edge-AI Processing
Work-in-Progress Poster Efficient Synaptic Delay Acceleration in Digital Event-Driven Neuromorphic Processors
Work-in-Progress Poster Representation-Independent Resubstitution for Area-Oriented Logic Optimization
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript MTL-Split: Multi-Task Learning for Edge Devices using Split Computing
Engineering Track Poster Die-Level Dynamic-IR Analysis Shift-Left Enabled by RedHawk-SC SigmaDVD
Engineering Track Poster A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
D
DAC Pavilion Panel From Design to Defense: Shaping the Future of Microelectronics Security
Work-in-Progress Poster A Multi-objective Optimization Framework of Spiking Neural Network and Neuromorphic Processor
Work-in-Progress Poster From RTL to Prompt: AN LLM-assisted Verification Methodology for General Processor
Work-in-Progress Poster NeuCore: A Novel Neuromorphic Processor Architecture with On-chip Event-driven Learning
Engineering Track Poster Design Enablement of 2D/3D Power-Thermal Self-Consistent Analysis
Research Manuscript Multiverse of Emerging Technologies for Computing and Optimization
Work-in-Progress Poster P-ReTi: Photonic Tensor Core for Real-Time Learning
Engineering Track Poster A module based automation for AXI performance monitoring, performance extraction and protocol checking.
Engineering Track Poster Plug-n-Play Testbench environment for ARM Coresight SoC-400
Research Manuscript NOFIS: Normalizing Flow for Rare Circuit Failure Analysis
Research Manuscript Duet: A Collaborative User Driven Recommendation System for Edge Devices
Back-End Design Design Automation Advancement in the Analog Domain
Back-End Design History, Present, and Future of STA: A Travel Through Timing
Engineering Track Poster A New Approach to Efficient Prelim Package Generation for Faster SOC Implementation
Back-End Design System Aware IO Integrity Signoff
Work-in-Progress Poster P-ReTi: Photonic Tensor Core for Real-Time Learning
Research Manuscript What's Your Best Side?
DAC Pavilion Panel Blackout – Managing kW Power Budgets
Research Manuscript Effective Quantum Resource Optimization via Circuit Resizing in BQSKit
Research Manuscript SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs
Research Manuscript Advanced Logic Synthesis - Improving Runtime and Quality
Work-in-Progress Poster Enhancing Delay-driven LUT Mapping with Boolean Decomposition
Late Breaking Results Poster Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration
Work-in-Progress Poster Representation-Independent Resubstitution for Area-Oriented Logic Optimization
Research Manuscript Unleashing the Power of T1-cells in SFQ Arithmetic Circuits
Engineering Track Poster Smart Testing: Integrating Fault Simulation and AI/ML for Efficient IP Validation
Engineering Track Poster SigmaDVD: High Coverage Solution for Power Integrity Signoff
Work-in-Progress Poster NeuroSteiner: A Graph Transformer for Wirelength Estimation
Engineering Track Poster Accelerate RF Board BOM Simulation with ADS Design Automation
Research Manuscript Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
Work-in-Progress Poster Stability Analysis of Integrated Circuits via Graph Neural Networks
Research Manuscript RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams
Work-in-Progress Poster A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
Research Manuscript Sharry：An Efficient and Sharing Far Memory System
Work-in-Progress Poster From RTL to Prompt: AN LLM-assisted Verification Methodology for General Processor
Work-in-Progress Poster Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
Engineering Track Poster Systematic Verification Framework for Memory Subsystem Ensuring Reliability and Robustness
Engineering Track Poster DVD-aware STA and its silicon correlation results on 10nm test chip
Work-in-Progress Poster SPHINCSLET - A Lightweight Implementation of SPHINCS+
Research Panel 3DIC Design Ecosystem – The Cats That Need Herding!
Research Manuscript MCU-Wide Timing Side Channels and Their Detection
Research Manuscript MCU-Wide Timing Side Channels and Their Detection
Engineering Track Poster Safeguarding datapath security requirements through formal verification
Work-in-Progress Poster Integrated MAC-based Systolic Arrays: Design and Performance Evaluation
Engineering Track Poster Automated Constraint Promotion Methodology from IP to SoC for Complex Designs
Engineering Track Poster Peak Power Optimization using Active Datapath Operator Profiling
Work-in-Progress Poster Confidential Computing with Heterogeneous Devices at Cloud-Scale
Work-in-Progress Poster Principles for Enabling TEEs on Domain-Specific Accelerators
Front-End Design AI co-pilot: Exploring the AI Frontier in Chip Design
Work-in-Progress Poster Compressed Latent Replays for Lightweight Continual Learning on Spiking Neural Networks
Research Panel Generative AI for Chip Design: Game Changer or Damp Squib?
Research Manuscript Levioso: Efficient Compiler-Informed Secure Speculation
Work-in-Progress Poster Scalable Multi-task Deep Inference on Resource Constrained Energy Harvesting System
Work-in-Progress Poster Zero-Space Cost Fault Tolerance for Transformer-based language models on ReRAM
Engineering Track Poster Advanced LLE aware Timing Signoff Methodology
Engineering Track Poster An Effective Method of Evaluating Chip Power Noise in System-level with iCPM
Engineering Track Poster An Efficient Early Thermal Management Solution in 3DIC design
Engineering Track Poster Electromagnetic Solutions From Design to Sign-Off Stage For High-Speed SerDes Design
Work-in-Progress Poster QPulse: Ansatz Design Analysis and Advantages of Parameterized Quantum Pulses
Work-in-Progress Poster RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
Work-in-Progress Poster Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
Research Manuscript New Frontiers in Hardware Security
Work-in-Progress Poster mROB: Multi-Level ReOrder Buffer Design with Reduced Area and Power
Work-in-Progress Poster nvmXR: Design Space Exploration of Non-Volatile Memory Architectures for Edge-XR Systems
Research Manuscript TAPMM:A Traffic-Aware Page Mapping Method for Multi-level NUMA Systems
Work-in-Progress Poster FOTA-Quant: FPGA-Oriented Token Adaptive Quantization Framework for the Acceleration of LLMs
Work-in-Progress Poster Additive Partial Sum Quantization
Research Manuscript EPIM: Efficient Processing-In-Memory Accelerators based on Epitome
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Late Breaking Results Poster Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Research Manuscript Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS
Work-in-Progress Poster ESFA: An Efficient Scalable FFT Accelerator Design Framework on Versal AI Engine
Research Manuscript Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
Research Manuscript PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
Work-in-Progress Poster Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction
Research Manuscript Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
Engineering Track Poster Physical Design With Intelligence
Research Manuscript Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA
Work-in-Progress Poster Eliminate control divergence in SpMV via in-SRAM reduction
Research Manuscript MCU-Wide Timing Side Channels and Their Detection
Engineering Track Poster Advancements in Source Synchronous Design Implementation: An EDA Perspective
Engineering Track Poster A Novel Flow to Verify SoC Integration with Formal Property Verification
Work-in-Progress Poster MatHE: A Near-Mat Processing In-Memory Accelerator for Fully Homomorphic Encryption
Engineering Track Poster A New Approach to Efficient Prelim Package Generation for Faster SOC Implementation
Engineering Track Poster Accelerating IO Liberty Generation through ML based Solution
Engineering Track Poster An Integrated Behavioral Modeling Method for Mixed Signal IPs
Back-End Design Design Automation Advancement in the Analog Domain
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Work-in-Progress Poster Defending Membership Inference Attack on Edge using Trusted Execution Environments
Work-in-Progress Poster Distributed Inference of DL Workloads on CIM-based Heterogeneous Accelerators
Research Manuscript Silicon Stairways: Climbing the Layers of 3D IC Innovation
Research Manuscript ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours
Front-End Design Formal CDC Glitch Check - Advanced Sign Off Solution
Research Manuscript Advanced gate-level glitch modeling using ANNs
Research Manuscript Execution Sequence Optimization for Processing In-Memory using Parallel Data Preparation
Research Manuscript On the Design of Novel Attention Mechanism for Enhanced Efficiency of Transformers
Research Manuscript Synthesis of Compact Flow-based Computing Circuits from Boolean Expressions
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DAC Pavilion Panel Blackout – Managing kW Power Budgets
Research Manuscript Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning
Research Manuscript Hyb-Learn: A Framework for On-Device Self-Supervised Continual Learning with Hybrid RRAM/SRAM Memory
Research Manuscript Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA
Research Manuscript AI Efficiency From Far Memory to Cross-Platform Performance
Research Manuscript ReCG: ReRAM-Accelerated Sparse Conjugate Gradient
Research Manuscript G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis
Work-in-Progress Poster ATAFAN: Design-Friendly Aging-aware Timing Analysis Framework Based on Hybrid Graph Network
Research Manuscript SymPhase: Phase Symbolization for Fast Simulation of Stabilizer Circuits
Research Manuscript Attacks and Defenses at Microarchitecture Level and Beyond
Research Manuscript GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package
Work-in-Progress Poster Pre-Silicon Power Side-channel Leakage Assessment of CRYSTALS-Kyber
Work-in-Progress Poster SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation
Work-in-Progress Poster TDM: Time and Distance based Metric for Quantifying Information Leakage Vulnerabilities in SoCs
Research Manuscript ChatPattern: Layout Pattern Customization via Natural Language
Research Manuscript SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs
Work-in-Progress Poster Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators
Research Manuscript An NTT/INTT Accelerator with Ultra-High Throughput and Area Efficiency for FHE
Work-in-Progress Poster Accelerating Large-scale Sparse LU Factorization for RF Circuit Simulation
Research Manuscript EPIM: Efficient Processing-In-Memory Accelerators based on Epitome
Research Manuscript Formally Verifying Arithmetic Chisel Designs for All Bit Widths at Once
Research Manuscript SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks
Work-in-Progress Poster Solving Maximum Flows of Undirected Graphs by Minimizing s-t Effective Resistances of Electrical Networks
Work-in-Progress Poster Stability Analysis of Integrated Circuits via Graph Neural Networks
Research Manuscript Data-driven HLS optimization for reconfigurable accelerators
Late Breaking Results Poster Late Breaking Results: Language-level QoR modeling for High-Level Synthesis
Work-in-Progress Poster A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Engineering Track Poster Accelerated Design Rule Learning for Silicon Photonics
Work-in-Progress Poster A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Research Manuscript Do-More-with-Less: Optimizing AI Models for Inference Efficiencies
Back-End Design Exploring Alternative Corridors for optimal routes
Engineering Track Poster Timing Closure Methods on 5nm Design Challenges
Engineering Track Poster SSN and EMA Bus Path Automation
Research Manuscript RISC-V Instruction Set Extensions for Multi-Precision Integer Arithmetic
Work-in-Progress Poster Distributed Inference of DL Workloads on CIM-based Heterogeneous Accelerators
Research Manuscript Learn and Fuzz!
Research Manuscript MTL-Split: Multi-Task Learning for Edge Devices using Split Computing
Engineering Track Poster An Integrated Behavioral Modeling Method for Mixed Signal IPs
Work-in-Progress Poster PCBench: A Dataset for Printed Circuit Board Routing
Work-in-Progress Poster Where and How to Charge: Effective Charging with Mobile Agent in Wireless Powered CPS
Research Manuscript Control Flow Divergence Optimization by Exploiting Tensor Cores
Work-in-Progress Poster A Crosstalk-Aware Timing Prediction Method in Routing
Work-in-Progress Poster PINN-based Compact Model for On-chip Silicon Photonic Devices
Late Breaking Results Poster Late Breaking Results: Extracting QNNs from NISQ Computers via Ensemble Learning
Research Manuscript TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer*
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Work-in-Progress Poster Integrated MAC-based Systolic Arrays: Design and Performance Evaluation
Work-in-Progress Poster MatHE: A Near-Mat Processing In-Memory Accelerator for Fully Homomorphic Encryption
Research Manuscript Control Flow Divergence Optimization by Exploiting Tensor Cores
Work-in-Progress Poster Hydrogen: Contention-Aware Hybrid Memory Management for Heterogeneous CPU-GPU Architectures
Late Breaking Results Poster Late Breaking Results: Circuit-Algorithm Co-design for Learnable Audio Analog Front-End
Research Manuscript NOFIS: Normalizing Flow for Rare Circuit Failure Analysis
Special Session (Research) Invited: Enabling AI-based Sensing with 5G Networks at the Edge
Research Manuscript GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
Engineering Track Poster A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
Engineering Track Poster Forward Progress Testing: Saftey vs Liveness Assertion
Research Manuscript An IP-Agnostic Foundational Cell Array Offering Supply Chain Security
Engineering Track Poster Faster Timing Closure of Multiple Power Domains Based Designs with SMVA
Research Panel Generative AI for Chip Design: Game Changer or Damp Squib?
Research Manuscript New Frontiers in Hardware Security
DAC Pavilion Panel A New Design Verification Era as Open-Source Upends the Status Quo
Engineering Track Poster An effective Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs
Work-in-Progress Poster Deputy NoC: A Case of Low Cost Network-on-Chip for Neural Network Accelerations on GPUs
Research Manuscript Advanced gate-level glitch modeling using ANNs
Research Manuscript LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
Late Breaking Results Poster Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Engineering Track Poster Coverage-based FV signoff – The complete cleanup methodology
Research Manuscript Efficient Bilevel Source Mask Optimization
Research Manuscript Knowing The Spec to Explore The Design via Transformed Bayesian Optimization
Research Manuscript LLM-HD: Layout Language Model for Hotspot Detection with GDS Semantic Encoding*
Work-in-Progress Poster Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-Memory
Research Manuscript QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference
Work-in-Progress Poster Mining signal temporal logic specifications for hybrid systems
Engineering Track Poster Smart Testing: Integrating Fault Simulation and AI/ML for Efficient IP Validation
Engineering Track Poster Advanced Static Methodology for Complete Connectivity and Glitch Signoff
Research Manuscript Deep Harmonic Finesse: Signal Separation in Wearable Systems with Limited Data
Work-in-Progress Poster HDFusion: Hierarchical Data Fusion for Robust Deep Tissue Sensing
Engineering Track Poster Enhanced State-Propagation based Vectorless IR-Drop Analysis Emulating Realistic Silicon Behavior
Work-in-Progress Poster GPU-Accelerated BFS for Dynamic Networks
Back-End Design Clock parameter tuning with an intelligent adaptive learning to improve performance and power of Multisource Clock Tree Synthesis
Engineering Track Poster Design Closure Methodology using stage wise checkers by Ease of Review to minimize Physical Design Implementation & Closure TAT
Engineering Track Poster Physical Design With Intelligence
Research Manuscript CircuitVAE: Efficient and Scalable Latent Circuit Optimization
Engineering Track Poster Virtual Instrumentation Based Predictive Checks for Shift-Left Low Power Verification
Engineering Track Poster Faster Timing Closure of Multiple Power Domains Based Designs with SMVA
Late Breaking Results Poster Late Breaking Results: Circuit-Algorithm Co-design for Learnable Audio Analog Front-End
Engineering Track Poster A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Work-in-Progress Poster Efficient Synaptic Delay Acceleration in Digital Event-Driven Neuromorphic Processors
Research Manuscript Duet: A Collaborative User Driven Recommendation System for Edge Devices
Work-in-Progress Poster Evergreen: Comprehensive Carbon Modeling for Performance-Emission Tradeoffs
Engineering Track Poster MODEL BASED SYSTEM SEMICONDUCTOR ENGINEERING
Work-in-Progress Poster AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs
Research Manuscript DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications
Research Manuscript RISC-V Instruction Set Extensions for Multi-Precision Integer Arithmetic
Late Breaking Results Poster Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Work-in-Progress Poster DOCTOR: Dynamic On-Chip Remediation Against Temporally-Drifting Thermal Variations Toward Self-Corrected Photonic Tensor Accelerators
Research Manuscript Field Programmable Quantum Array Compilation with Flying Ancillas
Work-in-Progress Poster RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
Work-in-Progress Poster Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
Research Manuscript A High-Throughput Private Inference Engine Based on 3D Stacked Memory
Back-End Design A New Frontier for Floorplanning with AI
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Engineering Track Poster Implementing World's First Fully Integrated SoC Solution For Direct-To-Satellite IoT Connectivity
Research Manuscript Heterogeneous and Reconfigurable Architecture: Applications and Tools
Research Manuscript Defending against Adversarial Patches using Dimensionality Reduction
Research Manuscript HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks
Research Manuscript GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis
Research Manuscript Ink: Efficient Incremental k-Critical Path Generation
Work-in-Progress Poster High-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory Region
Work-in-Progress Poster High-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory Region
Work-in-Progress Poster Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction
Research Manuscript Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
Work-in-Progress Poster DB-Hunter: Interactive-Guided Differential Testing for FPGA Simulation Debugger
Research Manuscript SMILE: LLC-based Shared Memory Expansion to Improve GPU Thread Level Parallelism
Work-in-Progress Poster SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration
Engineering Track Poster An Effective Method of Evaluating Chip Power Noise in System-level with iCPM
Work-in-Progress Poster Accelerating Large-scale Sparse LU Factorization for RF Circuit Simulation
Engineering Track Poster Coverage-based FV signoff – The complete cleanup methodology
Front-End Design Enhancing Formal Equivalence for Datapath Algorithms: A Proof Strategy with Intermediate Modeling to Address Structural Differences in Implementations
Engineering Track Poster Navigating Instruction Length Decode: TAP into IP using three pronged FV Trident
Engineering Track Poster Programmable IO Ring Builder and checker
Engineering Track Poster A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Engineering Track Poster Virtual Instrumentation Based Predictive Checks for Shift-Left Low Power Verification
Engineering Track Poster Enhanced State-Propagation based Vectorless IR-Drop Analysis Emulating Realistic Silicon Behavior
Engineering Track Poster Peak Power Optimization using Active Datapath Operator Profiling
Work-in-Progress Poster MatHE: A Near-Mat Processing In-Memory Accelerator for Fully Homomorphic Encryption
Engineering Track Poster Risk Management in Volume Diagnostics
H
Engineering Track Poster Empowering Early-Stage Design: An Automated Solution for Die Size Estimation and IO Ring Creation
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Work-in-Progress Poster Worst Case Response Time Analysis for Completely Fair Scheduling in Linux Systems
Analyst Presentation Chiplets – The next generation chip design trend beyond Moore’s Law
Research Manuscript GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package
Research Manuscript Conjuring: Leaking Control Flow via Speculative Fetch Attacks*
Research Manuscript Levioso: Efficient Compiler-Informed Secure Speculation
Research Manuscript A High-Performance Stochastic Simulated Bifurcation Ising Machine
Research Manuscript Efficient Approximate Decomposition Solver using Ising Model
Work-in-Progress Poster Hardware PDE Solvers Using Dynamic Stochastic Computing
Research Manuscript QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference
Engineering Track Poster Advanced LLE aware Timing Signoff Methodology
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Research Manuscript Field Programmable Quantum Array Compilation with Flying Ancillas
Work-in-Progress Poster RobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational Training
Work-in-Progress Poster Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
Work-in-Progress Poster FOTA-Quant: FPGA-Oriented Token Adaptive Quantization Framework for the Acceleration of LLMs
Research Manuscript Defending against Adversarial Patches using Dimensionality Reduction
Research Manuscript Foundation Models for EDA and Beyond
Research Manuscript ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model
Special Session (Research) Large Language Model - Revolutionizing the Entire Computing Paradigm
Work-in-Progress Poster PABTG: A Pipeline Architecture for Beaver Triple Generation in Secure Multi-party Computation
Research Manuscript Combining Parameterized Pulses and Contextual Subspace for More Practical VQE
Work-in-Progress Poster Accelerating Heterogeneous Workloads Using A Reconfigurable In-Memory Computing Architecture
Engineering Track Poster Automated Floorplan Scaling Solutions and Framework
Engineering Track Poster SSN and EMA Bus Path Automation
Engineering Track Poster An effective Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs
Research Manuscript Effective Quantum Resource Optimization via Circuit Resizing in BQSKit
Late Breaking Results Poster Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Research Manuscript Efficient Bilevel Source Mask Optimization
Work-in-Progress Poster Labidus: Productive Accelerator Development via Configurable Soft Processors
Research Manuscript DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications
Late Breaking Results Poster Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas
Work-in-Progress Poster Graph Attention Network-based Sparse Format Selection for Accelerating SpMM on GPUs
Work-in-Progress Poster mROB: Multi-Level ReOrder Buffer Design with Reduced Area and Power
Work-in-Progress Poster An Effective Timing Driven Placement with Accurate Differentiable Timing Approximation Integration
Work-in-Progress Poster SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration
Research Manuscript LLM-HD: Layout Language Model for Hotspot Detection with GDS Semantic Encoding*
Work-in-Progress Poster PCBench: A Dataset for Printed Circuit Board Routing
Research Manuscript Evaluating the Security of Logic Locking on Deep Neural Networks
Research Manuscript Deep Harmonic Finesse: Signal Separation in Wearable Systems with Limited Data
Research Manuscript HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks
Research Manuscript GNN-assisted Back-side Clock Routing Methodology for Advance Technologies
Back-End Design History, Present, and Future of STA: A Travel Through Timing
Engineering Track Poster Scalable modeling of dynamic voltage compression on timing
Embedded Systems and Software Edge Intelligence & GenAI: Exploring Challenges and Ethics
DAC Pavilion Panel Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Work-in-Progress Poster Optimization of DSP-Based Equalizer in High-Speed ADC-Based Receivers
Work-in-Progress Poster TinySeg: Memory-efficient Image Segmentation for Small Embedded Systems
Engineering Track Poster Advanced LLE aware Timing Signoff Methodology
Work-in-Progress Poster An Efficient Framework for High-Fidelity Automotive Exterior Design
Engineering Track Poster WatsonX and DDB for AI Based Design Analytics and Visualization
Research Manuscript Mixed-Dimensional Qudit State Preparation Using Edge-Weighted Decision Diagrams
Work-in-Progress Poster Quantifying the Energy Efficiency Benefits of Monolithic 3D Refreshless Embedded-DRAM
Research Manuscript DGR: Differentiable Global Router
Work-in-Progress Poster Deputy NoC: A Case of Low Cost Network-on-Chip for Neural Network Accelerations on GPUs
Research Manuscript G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Research Manuscript LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
Late Breaking Results Poster Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Research Manuscript NeuroSelect: Learning to Select Clauses in SAT Solvers
Late Breaking Results Poster Late Breaking Results: Wiring Reduction for Field-coupled Nanotechnologies
Work-in-Progress Poster Don't Cache, Speculate!: Speculative Address Translation for Flash-based Storage Systems
Engineering Track Poster Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Engineering Track Poster 3DIC prototype design and transient early thermal analysis
Engineering Track Poster Solving the antenna debug challenge in physical design verification
Engineering Track Poster Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Work-in-Progress Poster PINN-based Compact Model for On-chip Silicon Photonic Devices
Research Manuscript Low-Complexity Algorithmic Test Generation for Neuromorphic Chips
Research Manuscript Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes
Work-in-Progress Poster CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell Reprogramming
Research Manuscript Deep Reorganization: Retaining Residuals in TinyML
Research Manuscript Edgevolution: Transforming Edge Computing Paradigms
Work-in-Progress Poster Adaptive Neurosurgeon: DNN Computing Latency Minimization for Mobile Edge Intelligence
Work-in-Progress Poster A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
Engineering Track Poster AI-Enhanced Automated Optimization Workflow for HBM Interconnect on Interposer
Engineering Track Poster A "Shift-Left" Analysis Flow For Layout Parasitics Of High Speed Analog Mixed Signal Design
Research Manuscript Edgevolution: Transforming Edge Computing Paradigms
Late Breaking Results Poster Late Breaking Results: Circuit-Algorithm Co-design for Learnable Audio Analog Front-End
Work-in-Progress Poster Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-Memory
Research Manuscript Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption
Work-in-Progress Poster Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction
Research Manuscript Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
Research Manuscript TAPMM:A Traffic-Aware Page Mapping Method for Multi-level NUMA Systems
Research Manuscript Attacks and Defenses at Microarchitecture Level and Beyond
Late Breaking Results Poster Late Breaking Results: On the One-Key Premise of Logic Locking
Research Manuscript Accelerating Regular Path Queries over Graph Database with Processing-in-Memory
Work-in-Progress Poster RADAR: A Skew-resistant and Hotness-aware Ordered Index Design for Processing-in-memory Systems
Work-in-Progress Poster CIM for LLM: A Compute-In-Memory Architecture for Efficient Large Language Model Inference
Research Manuscript TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer*
Research Manuscript Low-Complexity Algorithmic Test Generation for Neuromorphic Chips
Work-in-Progress Poster RADAR: A Skew-resistant and Hotness-aware Ordered Index Design for Processing-in-memory Systems
Research Manuscript PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
Work-in-Progress Poster HPA: A novel IS-WS hybrid data flow for PIM architectures
Research Manuscript Accelerating Regular Path Queries over Graph Database with Processing-in-Memory
Work-in-Progress Poster RADAR: A Skew-resistant and Hotness-aware Ordered Index Design for Processing-in-memory Systems
Research Manuscript AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration
Research Manuscript An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology
Research Manuscript Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator
Work-in-Progress Poster DATIS: DRAM Architecture and Technology Integrated Simulation
Research Manuscript EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
Work-in-Progress Poster Zero-Space Cost Fault Tolerance for Transformer-based language models on ReRAM
Research Manuscript G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis
Research Manuscript G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Research Manuscript GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis
Research Manuscript Ink: Efficient Incremental k-Critical Path Generation
Work-in-Progress Poster Additive Partial Sum Quantization
Research Manuscript SMILE: LLC-based Shared Memory Expansion to Improve GPU Thread Level Parallelism
Engineering Track Poster A "Shift-Left" Analysis Flow For Layout Parasitics Of High Speed Analog Mixed Signal Design
Late Breaking Results Poster Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards
Research Manuscript Sharry：An Efficient and Sharing Far Memory System
Research Manuscript Net Resource Allocation: A Desirable Initial Routing Step
Research Manuscript PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
Research Manuscript Advanced Reinforcement Learning Algorithms to Optimize Design Verification
Work-in-Progress Poster RADAR: A Skew-resistant and Hotness-aware Ordered Index Design for Processing-in-memory Systems
Engineering Track Poster A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
Engineering Track Poster Simulation and Measurement of MOMCAP Breakdown Risk Based on TCAD
Late Breaking Results Poster Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints
Work-in-Progress Poster SVDE: Serverless System for Low-Latency Video Analytic Queries Using Tree-based Regression
I
Research Manuscript Effective Quantum Resource Optimization via Circuit Resizing in BQSKit
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Work-in-Progress Poster SFQ counter-based precomputation for large-scale cryogenic VQE machines
Research Panel 3DIC Design Ecosystem – The Cats That Need Herding!
Research Manuscript What's Your Best Side?
Work-in-Progress Poster An Application of Information Flow Tracking to Hardware Trojan Detection
Work-in-Progress Poster SFQ counter-based precomputation for large-scale cryogenic VQE machines
Special Session (Research) Emerging Technologies for Energy-efficient Neuromorphic Edge Computing
Research Manuscript DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications
Work-in-Progress Poster An Application of Information Flow Tracking to Hardware Trojan Detection
Work-in-Progress Poster Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)
Work-in-Progress Poster Scalable Multi-task Deep Inference on Resource Constrained Energy Harvesting System
Research Manuscript CLUMAP: Clustered Mapper for CGRAs with Predication
Special Session (Research) Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip
Late Breaking Results Poster Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas
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Engineering Track Poster Holistic Approach on 3DIC Planning
Engineering Track Poster Pnr implementation challenges in 3d ic
Engineering Track Poster An uptick on Automotive Safety Solutions using Cadence Implementation Tools
Engineering Track Poster Redefining Hierarchical Power Integrity signoff for Ultra-Large System-on-Chips
Engineering Track Poster Programmable IO Ring Builder and checker
Engineering Track Poster Charting Uncharted Waters: Functional Simulation Reshaping CDC/RDC Constraints Signoff
Research Manuscript Some Things are Best Left In/Near Memories
Work-in-Progress Poster Defending Membership Inference Attack on Edge using Trusted Execution Environments
Engineering Track Poster Programmable IO Ring Builder and checker
Engineering Track Poster Physical Design With Intelligence
Work-in-Progress Poster Agile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous Era
Work-in-Progress Poster Quantifying the Energy Efficiency Benefits of Monolithic 3D Refreshless Embedded-DRAM
Work-in-Progress Poster Libra: Collaborating with Basis-Inverted Circuits to Mitigate State-Dependent Errors on NISQ Programs
Work-in-Progress Poster PIANIST: Efficient Quantum Circuit Simulation using Commercial Processing-in-Memory System
Work-in-Progress Poster Retract: Logarithmic-Depth Reconstruction of Continuous Controlled-NOT Logic Block
Engineering Track Poster A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
Engineering Track Poster Achieving High Local Noise Coverage in Dynamic EMIR Analysis using SigmaDVD
Engineering Track Poster Novel Way of Checking and Analyzing Peak to Peak Voltage Variation Challenges for High Computational Multiprocessors SOC
Engineering Track Poster Redefining Hierarchical Power Integrity signoff for Ultra-Large System-on-Chips
Research Manuscript Formally Verifying Arithmetic Chisel Designs for All Bit Widths at Once
Engineering Track Poster Developing Software Test Library (STL) as a Safety Mechanism for Vision AI DSP
Back-End Design A Systematic Approach to 3D Cutline Exploration and Benchmarking
Embedded Systems and Software No-Code Power and Clock System Design
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Work-in-Progress Poster Worst Case Response Time Analysis for Completely Fair Scheduling in Linux Systems
Work-in-Progress Poster An instant leafcell layout auto-generator for area compact memory design automation
Work-in-Progress Poster Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation
Research Manuscript Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Late Breaking Results Poster Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Engineering Track Poster Executable Tables, 'A Journey from Document to Simulation Capable, Exemplified Using DDR5 '
Research Manuscript Execution Sequence Optimization for Processing In-Memory using Parallel Data Preparation
Research Manuscript On the Design of Novel Attention Mechanism for Enhanced Efficiency of Transformers
Research Manuscript Synthesis of Compact Flow-based Computing Circuits from Boolean Expressions
Work-in-Progress Poster ATAFAN: Design-Friendly Aging-aware Timing Analysis Framework Based on Hybrid Graph Network
Work-in-Progress Poster DATIS: DRAM Architecture and Technology Integrated Simulation
Research Manuscript Empowering Edge Intelligence: When IoT Devices Meet AI
Work-in-Progress Poster Accelerating Large-scale Sparse LU Factorization for RF Circuit Simulation
Research Manuscript Size-Optimized Depth-Constrained Large Parallel Prefix Circuits
Work-in-Progress Poster Addressing the Diversity in AI Computing: An On-chip Programmable Accelerator
Work-in-Progress Poster DB-Hunter: Interactive-Guided Differential Testing for FPGA Simulation Debugger
Research Manuscript QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference
Special Session (Research) EDA for Heterogeneous Integration: What Lies Ahead?
Research Manuscript Boolean Matching Reversible Circuits: Algorithm and Complexity
Research Manuscript TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer*
Work-in-Progress Poster A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
Research Manuscript FHE-CGRA: Enable Efficient Acceleration of Fully Homomorphic Encryption on CGRAs
Research Manuscript G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Work-in-Progress Poster Distribution-Guided Fairness Calibration in Learning
Research Manuscript Control Flow Divergence Optimization by Exploiting Tensor Cores
Research Manuscript Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation
Research Manuscript PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning
Research Manuscript Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing
Research Manuscript AccMoS: Accelerating Model Simulation for Simulink via Code Generation
Research Manuscript CFTCG: Test Case Generation for Simulink Model through Code Based Fuzzing
Research Manuscript Effectively Sanitizing Embedded Operating Systems
Work-in-Progress Poster A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
Research Manuscript CDA-GNN: A Chain-driven Accelerator for Efficient Asynchronous Graph Neural Network
Research Manuscript High-Performance and Resource-Efficient Dynamic Memory Management in High-Level Synthesis
Research Manuscript RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference
Work-in-Progress Poster A Crosstalk-Aware Timing Prediction Method in Routing
Work-in-Progress Poster High-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory Region
Research Manuscript LIVAK: A High-Performance In-Memory Learned Index for Variable-Length Keys
Work-in-Progress Poster Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction
Research Manuscript Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR
Work-in-Progress Poster Accelerating Large-scale Sparse LU Factorization for RF Circuit Simulation
Research Manuscript MASC: A Memory-Efficient Adjoint Sensitivity Analysis through Compression Using Novel Spatiotemporal Prediction
Research Manuscript MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction
Research Manuscript Powering the Future: From Modeling, Simulation to Prediction
Research Manuscript ReCG: ReRAM-Accelerated Sparse Conjugate Gradient
Engineering Track Poster Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Work-in-Progress Poster An instant leafcell layout auto-generator for area compact memory design automation
Engineering Track Poster Challenges Faced in Formal Based MSI: Tackle Formal Problem with a Formal Solution
Engineering Track Poster A Novel Automation flow to generate SV-UVM Testbench with integrated BFMs
Back-End Design System Aware IO Integrity Signoff
DAC Pavilion Panel A New Design Verification Era as Open-Source Upends the Status Quo
Work-in-Progress Poster LEAP: Layout aware Estimation of Analog design Parasitics
Engineering Track Poster DIGITAL CONTINUITY FROM SEMICONDUCTOR EBOM TO MBOM AND BILL OF PROCESS
Engineering Track Poster MODEL BASED SYSTEM SEMICONDUCTOR ENGINEERING
Engineering Track Poster On Cloud Secured Collaboration From chips to embedded systems
Exhibitor Forum On Cloud Semiconductor Virtual Twin Experience Universe
Research Manuscript Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Engineering Track Poster Powerdash: A Comprehensive Framework for SOC Power Analysis and Tracking
Research Manuscript Cache-aware Task Decomposition for Efficient Intermittent Computing Systems
Research Manuscript FHE-CGRA: Enable Efficient Acceleration of Fully Homomorphic Encryption on CGRAs
Engineering Track Poster A Data-Driven Automation Method of Liberty Model Characterization for Custom Cells
Work-in-Progress Poster Labidus: Productive Accelerator Development via Configurable Soft Processors
Engineering Track Poster DVD-aware STA and its silicon correlation results on 10nm test chip
Engineering Track Poster Early Validation of Random TB using Formal Technology
Work-in-Progress Poster Dual-Axis ECC: Vertical and Horizontal error correction
Work-in-Progress Poster Affinity-based Optimizations of Homomorphic Encryption Operations on Processing-in-DRAM
Research Manuscript Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Engineering Track Poster DVD-aware STA and its silicon correlation results on 10nm test chip
Engineering Track Poster 3DIC prototype design and transient early thermal analysis
Engineering Track Poster High Coverage QA for Process Variability Compensation in LVS Rule Deck
Work-in-Progress Poster SeGen: Automatic Topology Generator of Sequencing Element
Research Manuscript VVIP: Versatile Vertical Indexing Processor for Edge Computing
K
Engineering Track Poster Struct Based Lower Level Modelling Using SystemVerilog UDT for Verification of Power Management IC
Research Manuscript PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs
Work-in-Progress Poster Eliminate control divergence in SpMV via in-SRAM reduction
Work-in-Progress Poster Escaping local optima in global placement
Engineering Track Poster Coverage-based FV signoff – The complete cleanup methodology
Research Manuscript Data-driven HLS optimization for reconfigurable accelerators
Back-End Design History, Present, and Future of STA: A Travel Through Timing
Engineering Track Poster WatsonX and DDB for AI Based Design Analytics and Visualization
Engineering Track Poster A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Research Manuscript C-Nash: A Novel Ferroelectric Computing-in-Memory Architecture for Solving Mixed Strategy Nash Equilibrium
Research Manuscript Energy Efficient Dual Designs of FeFET-Based Analog In-Memory Computing with Inherent Shift-Add Capability
Work-in-Progress Poster An Application of Information Flow Tracking to Hardware Trojan Detection
Research Manuscript Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection
Research Manuscript Deep Reorganization: Retaining Residuals in TinyML
Engineering Track Poster Globalized bulk biasing based substrate noise reducing method for size reduction in digital circuit
Work-in-Progress Poster SeGen: Automatic Topology Generator of Sequencing Element
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Engineering Track Poster Dashboard Model for Foundry Early Node Assessments using Synopsys Design.da
Late Breaking Results Poster Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas
Research Manuscript HiLight: A Comprehensive Framework For High Performance And Light-Weight Scalability In Surface Code Communication
Research Manuscript PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs
Research Manuscript RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers
Research Manuscript SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation
Research Manuscript Where Processing-in-Memory Fits Best in the System
Work-in-Progress Poster Labidus: Productive Accelerator Development via Configurable Soft Processors
Work-in-Progress Poster A General Purpose IMC Architecture with ADC-Awared Neural Networks
Work-in-Progress Poster Worst Case Response Time Analysis for Completely Fair Scheduling in Linux Systems
Front-End Design Systematic Flow on AC Scan Timing/ATPG Constraint Generation
Engineering Track Poster Systematic Flow on AC Scan Timing/ATPG Constraint Generation
Engineering Track Poster Powerdash: A Comprehensive Framework for SOC Power Analysis and Tracking
Work-in-Progress Poster SPHINCSLET - A Lightweight Implementation of SPHINCS+
Research Manuscript Deep Harmonic Finesse: Signal Separation in Wearable Systems with Limited Data
Work-in-Progress Poster HDFusion: Hierarchical Data Fusion for Robust Deep Tissue Sensing
Engineering Track Poster An efficient QA methodology for SRAM libraries
Engineering Track Poster Solving the antenna debug challenge in physical design verification
Engineering Track Poster A Novel Automation flow to generate SV-UVM Testbench with integrated BFMs
Research Manuscript Uncovering Software-Based Power Side-Channel Attacks on Apple M1/M2 Systems
Work-in-Progress Poster DRL-based Voltage Optimization for Multiple Droplet Routing in DMFBs
Engineering Track Poster Ask-EDA: A conversational agent for tools, methodology, technology and design problems
Work-in-Progress Poster CIM for LLM: A Compute-In-Memory Architecture for Efficient Large Language Model Inference
Research Manuscript Transforming Transformers: Accelerating Transformer Models for ViT and LLMs
Engineering Track Poster WatsonX and DDB for AI Based Design Analytics and Visualization
Research Manuscript SAS - A Framework for Symmetry-based Approximate Synthesis
Research Manuscript EPIM: Efficient Processing-In-Memory Accelerators based on Epitome
Work-in-Progress Poster GL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration Method
Research Manuscript SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs
Work-in-Progress Poster Reset Domain Crossing Design Verification Closure using Advanced Data Analytics Techniques
Engineering Track Poster Automated Place and Route based solution for Custom Blocks
Engineering Track Poster A Novel approach to implement FuSA Feature in Complex Automotive SoCs Using USF
Work-in-Progress Poster H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications
Research Manuscript Memories Have a Mind of Their Own
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Work-in-Progress Poster NeuroSteiner: A Graph Transformer for Wirelength Estimation
Research Manuscript HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks
Embedded Systems and Software No-Code Power and Clock System Design
Engineering Track Poster Globalized bulk biasing based substrate noise reducing method for size reduction in digital circuit
Work-in-Progress Poster PIANIST: Efficient Quantum Circuit Simulation using Commercial Processing-in-Memory System
Research Manuscript VVIP: Versatile Vertical Indexing Processor for Edge Computing
Engineering Track Poster Design Methodologies for Minimizing Local Routing Congestions in Low-level Metal Layers
Work-in-Progress Poster Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation
Engineering Track Poster Methodology of linking the LDR and DRC code by automatically generated test pattern
Research Manuscript Nona: Accurate Power Prediction Model Using Neural Networks
Work-in-Progress Poster Optimization of DSP-Based Equalizer in High-Speed ADC-Based Receivers
Research Manuscript Challenging the Autonomy Challenges
Work-in-Progress Poster Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation
Work-in-Progress Poster Don't Cache, Speculate!: Speculative Address Translation for Flash-based Storage Systems
Embedded Systems and Software No-Code Power and Clock System Design
Engineering Track Poster DVD-aware STA and its silicon correlation results on 10nm test chip
Work-in-Progress Poster TinySeg: Memory-efficient Image Segmentation for Small Embedded Systems
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Engineering Track Poster Flash-based storage systems exploiting the data period for performance and security enhancement
Back-End Design ML based PPA Push using DRV Prediction
Work-in-Progress Poster Dual-Axis ECC: Vertical and Horizontal error correction
Engineering Track Poster 3DIC prototype design and transient early thermal analysis
Back-End Design ML based PPA Push using DRV Prediction
Engineering Track Poster Unified Waveform Analysis Platform for Tr.-Level Design Verification
Engineering Track Poster Methodology of linking the LDR and DRC code by automatically generated test pattern
Engineering Track Poster Design Methodologies for Minimizing Local Routing Congestions in Low-level Metal Layers
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Work-in-Progress Poster Dual-Axis ECC: Vertical and Horizontal error correction
Engineering Track Poster 3DIC prototype design and transient early thermal analysis
Engineering Track Poster Design Methodologies for Minimizing Local Routing Congestions in Low-level Metal Layers
Back-End Design ML based PPA Push using DRV Prediction
Work-in-Progress Poster Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation
Work-in-Progress Poster Don't Cache, Speculate!: Speculative Address Translation for Flash-based Storage Systems
Engineering Track Poster A Heuristic-Based Routing Methodology for Block-Level Memory Layout Routability Enhancement
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Engineering Track Poster Flash-based storage systems exploiting the data period for performance and security enhancement
Back-End Design ML based PPA Push using DRV Prediction
Research Manuscript STCO for Embedded Compute in Memory Devices and Circuits
Research Manuscript MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
Back-End Design ML based PPA Push using DRV Prediction
Research Manuscript Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Engineering Track Poster A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Engineering Track Poster Advanced LLE aware Timing Signoff Methodology
Engineering Track Poster Methodology of linking the LDR and DRC code by automatically generated test pattern
Engineering Track Poster Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Engineering Track Poster A Decade of Evolution in Formal Verification
Research Manuscript CircuitVAE: Efficient and Scalable Latent Circuit Optimization
Research Manuscript Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Research Manuscript Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Work-in-Progress Poster QPulse: Ansatz Design Analysis and Advantages of Parameterized Quantum Pulses
Research Manuscript Triplet Network-Based DNA Encoding for Enhanced Similarity Image Retrieval
Engineering Track Poster An efficient QA methodology for SRAM libraries
Work-in-Progress Poster Quantifying the Energy Efficiency Benefits of Monolithic 3D Refreshless Embedded-DRAM
Work-in-Progress Poster Are Adversarial Examples Suitable To Be Test Suites for Testing Deep Neural Networks
Work-in-Progress Poster RADAR: A Skew-resistant and Hotness-aware Ordered Index Design for Processing-in-memory Systems
Work-in-Progress Poster FOTA-Quant: FPGA-Oriented Token Adaptive Quantization Framework for the Acceleration of LLMs
Work-in-Progress Poster Efficient Synaptic Delay Acceleration in Digital Event-Driven Neuromorphic Processors
Engineering Track Poster High Coverage QA for Process Variability Compensation in LVS Rule Deck
Back-End Design A New Frontier for Floorplanning with AI
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Engineering Track Poster Implementing World's First Fully Integrated SoC Solution For Direct-To-Satellite IoT Connectivity
Research Manuscript QMark: Robust Watermarks for IP Protection of Quantized Large Language Models
Work-in-Progress Poster A verification plan to assess the quality of mobile telephony in Brazil
DAC Pavilion Panel Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems
DAC Pavilion Panel Cooley's DAC Troublemaker Panel
Research Manuscript The Next Step to Efficient AI: Number Formats, Quantization and Beyond
DAC Pavilion Panel Advancing Chip Security to Meet Heightened Requirements
Work-in-Progress Poster Quantifying the Energy Efficiency Benefits of Monolithic 3D Refreshless Embedded-DRAM
Engineering Track Poster DVD-aware STA and its silicon correlation results on 10nm test chip
Research Panel 3DIC Design Ecosystem – The Cats That Need Herding!
Engineering Track Poster A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
Engineering Track Poster Next-Gen comprehensive IR analysis with Ansys SigmaAV
Engineering Track Poster Redefining Hierarchical Power Integrity signoff for Ultra-Large System-on-Chips
Engineering Track Poster Modeling Optimal Number of Tap-points for Flexible H-tree During Clock Tree Synthesis
Engineering Track Poster LINKED LIST PROOF ACCELERATOR
Engineering Track Poster Challenges and Improvements in StandardCell OpenAccess Content for Analog Design
Work-in-Progress Poster Integrated MAC-based Systolic Arrays: Design and Performance Evaluation
Engineering Track Poster A Novel methodology for re-simulation of block vectors helping validate Power Optimization QoR 20x faster
Engineering Track Poster Peak Power Optimization using Active Datapath Operator Profiling
Engineering Track Poster Programmable IO Ring Builder and checker
Engineering Track Poster An Integrated Behavioral Modeling Method for Mixed Signal IPs
Engineering Track Poster An Integrated Behavioral Modeling Method for Mixed Signal IPs
Engineering Track Poster Autonomous Power Sequence validation solution for I/O using Solido Design Environment
Engineering Track Poster Struct Based Lower Level Modelling Using SystemVerilog UDT for Verification of Power Management IC
Engineering Track Poster Automated Place and Route based solution for Custom Blocks
Engineering Track Poster Physical Design With Intelligence
Research Manuscript PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs
Research Manuscript MCU-Wide Timing Side Channels and Their Detection
Research Manuscript How to Steal CPU Idle Time When Synchronous I/O Mode Becomes Promising
Research Manuscript CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis
Engineering Track Poster Globalized bulk biasing based substrate noise reducing method for size reduction in digital circuit
Research Manuscript RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers
Research Manuscript Data-driven HLS optimization for reconfigurable accelerators
L
Engineering Track Poster Calibre Autowaiver for Early DRC & DFM Analysis In Big Die Designs
Engineering Track Poster Holistic Approach on 3DIC Planning
Engineering Track Poster Struct Based Lower Level Modelling Using SystemVerilog UDT for Verification of Power Management IC
Work-in-Progress Poster Accelerating Range-Joins for Big Data Genomic Variant Annotation on HBM-enabled FPGAs
Work-in-Progress Poster An Efficient Framework for High-Fidelity Automotive Exterior Design
Engineering Track Poster Overcoming the Growing Challenge of IR Drop by Effective Power Grid Enhancement during Chip Finishing
Engineering Track Poster Solving the antenna debug challenge in physical design verification
Engineering Track Poster The Designer's Superpower! Early Circuit Verification with Calibre nmLVS Recon
Research Manuscript Design of a Quantum Walk Circuit to Solve the Subset-Sum Problem
Work-in-Progress Poster Approx-T: Design Methodology for Approximate Multiplication Units via Taylor-expansion
Engineering Track Poster Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Engineering Track Poster Dashboard Model for Foundry Early Node Assessments using Synopsys Design.da
Engineering Track Poster Methodology of linking the LDR and DRC code by automatically generated test pattern
Engineering Track Poster 3DIC prototype design and transient early thermal analysis
Engineering Track Poster DVD-aware STA and its silicon correlation results on 10nm test chip
Work-in-Progress Poster CIM for LLM: A Compute-In-Memory Architecture for Efficient Large Language Model Inference
Work-in-Progress Poster PIANIST: Efficient Quantum Circuit Simulation using Commercial Processing-in-Memory System
Embedded Systems and Software Functional Accuracy Enhancement of In-House Virtual Platform using Commercial IP Model
Research Manuscript MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models
Work-in-Progress Poster A Practical DRAM-based Analog PIM Architecture
Engineering Track Poster Bus Delay Skew Minimization for High Bandwidth Memory Designs
Engineering Track Poster Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Engineering Track Poster A Novel Methodology for Library Characterization and Modeling Considering Local Layout Effect
Engineering Track Poster Advanced LLE aware Timing Signoff Methodology
Embedded Systems and Software No-Code Power and Clock System Design
Work-in-Progress Poster Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation
Research Manuscript Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs
Research Manuscript Complexity Matters: Scheduling and Accelerating Data Structures in DNNs
Back-End Design ML based PPA Push using DRV Prediction
Work-in-Progress Poster Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation
Engineering Track Poster A Heuristic-Based Routing Methodology for Block-Level Memory Layout Routability Enhancement
Engineering Track Poster Row-Based Placement and Legalization for Mixed Signal Power Delivery IP in Memory
Late Breaking Results Poster Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration
Work-in-Progress Poster Representation-Independent Resubstitution for Area-Oriented Logic Optimization
Embedded Systems and Software Automated Generation of SSD Stress Tests Using Offline Reinforcement Learning
Research Manuscript G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis
Research Manuscript G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner
Engineering Track Poster High Coverage QA for Process Variability Compensation in LVS Rule Deck
Work-in-Progress Poster SPHINCSLET - A Lightweight Implementation of SPHINCS+
Work-in-Progress Poster Optimization of DSP-Based Equalizer in High-Speed ADC-Based Receivers
Engineering Track Poster CDC Simulation Checker Implementation for Constant and Quasi-static Data Paths
Engineering Track Poster High Coverage QA for Process Variability Compensation in LVS Rule Deck
Front-End Design AI co-pilot: Exploring the AI Frontier in Chip Design
Work-in-Progress Poster Scalable Multi-task Deep Inference on Resource Constrained Energy Harvesting System
Engineering Track Poster A Novel Automation flow to generate SV-UVM Testbench with integrated BFMs
Back-End Design Automatic Layout Symmetry Annotation via Graph Node Embeddings
Late Breaking Results Poster Late Breaking Results: Circuit-Algorithm Co-design for Learnable Audio Analog Front-End
Work-in-Progress Poster NeuroSteiner: A Graph Transformer for Wirelength Estimation
Back-End Design Automatic Layout Symmetry Annotation via Graph Node Embeddings
Research Manuscript Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
Work-in-Progress Poster Zero-Space Cost Fault Tolerance for Transformer-based language models on ReRAM
Work-in-Progress Poster Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction
Research Manuscript Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
Work-in-Progress Poster Transformer-QEC: Quantum Error Correction Code Decoding with Transferable Transformers
Research Manuscript Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
Special Session (Research) AI Technologies Meet Quantum Computing
Research Manuscript Fast Virtual Gate Extraction For Silicon Quantum Dot Devices
Work-in-Progress Poster PCBench: A Dataset for Printed Circuit Board Routing
Research Manuscript Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption
Research Manuscript Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
Research Manuscript Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Research Manuscript Low-Complexity Algorithmic Test Generation for Neuromorphic Chips
Work-in-Progress Poster Exploring Distributed Circuit Design Using Single-Step Reinforcement Learning
Work-in-Progress Poster B-Ring:An Efficient Interleaved Bidirectional Ring All-reduce Algorithm for Gradient Synchronization
Research Manuscript TAPMM:A Traffic-Aware Page Mapping Method for Multi-level NUMA Systems
Research Manuscript zeroTT: A Two-Step State Transition Avoidance Scheme for MLC STT-RAM
Work-in-Progress Poster HRing: A Hierarchical Ring Design Method for Wavelength-Routed Optical Networks-on-Chip
Research Manuscript LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design
Late Breaking Results Poster Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI)
Work-in-Progress Poster Accelerating Large-scale Sparse LU Factorization for RF Circuit Simulation
Research Manuscript Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip
Work-in-Progress Poster A Divide-and-conquer Pebbling Strategy for Oracle Synthesis in Quantum Computing
Research Manuscript ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours
Research Manuscript PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
Work-in-Progress Poster HPA: A novel IS-WS hybrid data flow for PIM architectures
Research Manuscript Combining Parameterized Pulses and Contextual Subspace for More Practical VQE
Work-in-Progress Poster QPulse: Ansatz Design Analysis and Advantages of Parameterized Quantum Pulses
Research Manuscript DGR: Differentiable Global Router
Research Manuscript ElasticZRAM: Revisiting ZRAM for Swapping on Mobile Devices
Work-in-Progress Poster DB-Hunter: Interactive-Guided Differential Testing for FPGA Simulation Debugger
Work-in-Progress Poster PABTG: A Pipeline Architecture for Beaver Triple Generation in Secure Multi-party Computation
Research Manuscript Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption
Work-in-Progress Poster Athena: Add More Intelligence to RMT-based Network Data Plane with Low-bit Quantization
Research Manuscript Chiplever: Towards Effortless Extension of Chiplet-based System for FHE
Research Manuscript Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse
Research Manuscript Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Research Manuscript Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR
Work-in-Progress Poster Automated Generation of OoO ASIP from ISA Documents via Nano-Operator Abstraction
Research Manuscript Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation
Work-in-Progress Poster Circuit Transformer: End-to-end Logic Synthesis by Predicting the Next Gate
Work-in-Progress Poster Circuit Transformer: End-to-end Logic Synthesis by Predicting the Next Gate
Work-in-Progress Poster ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
Research Manuscript A Software-Hardware Co-design Solution for 3D Inner Structure Reconstruction
Research Manuscript Net Resource Allocation: A Desirable Initial Routing Step