Presentation
AutoDV: AI-Generated HDL with Design Verification In-The-Loop
DescriptionArtificial Intelligence (AI), particularly Large Language Models (LLMs), has revolutionized the landscape of Hardware Description Language (HDL) generation in digital design. This breakthrough technology holds immense promise for streamlining design processes and accelerating innovation. However, the probabilistic nature of LLMs poses unique challenges in HDL generation, frequently leading to inaccurate code predictions. This is a crucial concern in hardware design, where precision is paramount.
To address this critical challenge, we introduce AutoDV, an innovative LLM-based architecture designed to enhance the precision and reliability of AI-generated HDL code. At its core lies a system of interconnected, specialized, and compact LLMs, each meticulously crafted to handle specific aspects of the HDL generation process. This approach not only enables AutoDV to leverage the collective strengths of individual LLMs, but also fosters synergistic interactions among them.
AutoDV's groundbreaking capabilities stem from its two key components: the capability of automatically interfacing with external verification tools and a comprehensive library of pre-defined IPs. By seamlessly interfacing with established verification tools, AutoDV ensures rigorous Design Verification (DV), minimizing the risk of propagating errors to subsequent design stages. Additionally, AutoDV's IP library empowers LLMs to directly access and utilize these well-established and rigorously verified design components, significantly elevating the accuracy of the generated HDL code.
In this presentation, we will explore the technical underpinnings of AutoDV, beginning with an overview of its architecture and then examining the synergism between its components. The presentation will conclude with a practical demonstration.
To address this critical challenge, we introduce AutoDV, an innovative LLM-based architecture designed to enhance the precision and reliability of AI-generated HDL code. At its core lies a system of interconnected, specialized, and compact LLMs, each meticulously crafted to handle specific aspects of the HDL generation process. This approach not only enables AutoDV to leverage the collective strengths of individual LLMs, but also fosters synergistic interactions among them.
AutoDV's groundbreaking capabilities stem from its two key components: the capability of automatically interfacing with external verification tools and a comprehensive library of pre-defined IPs. By seamlessly interfacing with established verification tools, AutoDV ensures rigorous Design Verification (DV), minimizing the risk of propagating errors to subsequent design stages. Additionally, AutoDV's IP library empowers LLMs to directly access and utilize these well-established and rigorously verified design components, significantly elevating the accuracy of the generated HDL code.
In this presentation, we will explore the technical underpinnings of AutoDV, beginning with an overview of its architecture and then examining the synergism between its components. The presentation will conclude with a practical demonstration.
Event Type
Exhibitor Forum
TimeTuesday, June 253:30pm - 4:00pm PDT
LocationExhibitor Forum, Level 1 Exhibit Hall
AI