Presentation
Complex application mapping to heterogeneous compute resources
DescriptionToday's embedded system application architects face the challenge of mapping to increasingly diverse compute resources including CPUs, AIEs, and FPGA accelerators. The architect must manage the mapping of the application to these compute resources while also considering details like data movement, memory structures, and data types. This results in a complex trade-space analysis of how to optimally map an application to a heterogeneous target such as the Versal FPGA SoC.
This technical talk will outline the existing system architect workflows and shows a gap in today's SoC tools for supporting the system architect in evaluating their application mapping trade space analysis. The proposed "application explorer" tool supporting the system architect in the early analysis of application mapping to major compute resource types based on a system level stochastic model simulation. This model-based system engineering tool facilitating the system architect to iterate different design mappings and ultimately provide downstream detailed implementation teams with a definition of the scope of their functionality. The talk will then present a prototype of the concept implemented as an extension to the Mirabilis VisualSim Architect tool for a signal processing algorithm that targets a Versal FPGA SoC.
This technical talk will outline the existing system architect workflows and shows a gap in today's SoC tools for supporting the system architect in evaluating their application mapping trade space analysis. The proposed "application explorer" tool supporting the system architect in the early analysis of application mapping to major compute resource types based on a system level stochastic model simulation. This model-based system engineering tool facilitating the system architect to iterate different design mappings and ultimately provide downstream detailed implementation teams with a definition of the scope of their functionality. The talk will then present a prototype of the concept implemented as an extension to the Mirabilis VisualSim Architect tool for a signal processing algorithm that targets a Versal FPGA SoC.
Event Type
Embedded Systems and Software
TimeWednesday, June 262:06pm - 2:24pm PDT
Location2010, 2nd Floor
AI
Embedded Systems
Engineering Tracks