Presentation
OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-offs
DescriptionIn-SRAM computing promises energy efficiency, but circuit nonlinearities and PVT variations pose major challenges in designing robust accelerators. To address this, we introduce OPTIMA, a modeling framework that aids in analyzing bit-line discharge and power consumption in 6T-SRAM-based accelerators. It provides insights into limiting factors and enables fast design-space exploration of circuit configurations. Leveraging OPTIMA for in-SRAM multiplications exhibits ∼100× simulation speed-up while maintaining an average modeling error of 0.56mV. Exploration yields an optimized multiplier with 1.02pJ energy consumption per 4-bit operation and classification accuracies of 71.91% (top-1) and 90.72% (top-5) for ImageNet and 92.57% for CIFAR-10 datasets respectively when applied in quantized DNNs.
Event Type
Research Manuscript
TimeWednesday, June 265:12pm - 5:29pm PDT
Location3004, 3rd Floor
Design
In-memory and Near-memory Computing Architectures, Applications and Systems