Presentation
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption
DescriptionLong DRAM access latency has a significant impact on modern system performance. However, the improvement of access latency is limited as the DRAM vendors reserve considerable timing margins against seldom worst-case conditions. To mitigate such pessimistic timing margins, we propose a temperature- and process-variation-aware timing detection and adaption DRAM (TPDA-DRAM) architecture. It equips in-situ cross-coupled detectors to monitor the voltage difference between bitline pairs, enabling estimation of timing margins caused by process and temperature variations. Moreover, TPDA-DRAM incorporates two collaborative timing adaption schemes: 1) a process-variation-aware timing adaption scheme (PVA) that selectively accelerates the access to rare weak cells and 2) a temperature-variation-aware timing adaption scheme (TVA) that precisely adjust timing parameters by adopting temperature information. Compared to prior art, the proposed detector reduces detection deviation by 54.8% and area overhead by 88.1%. The system-level evaluation in an eight-core system shows that TPDA-DRAM improves the average performance and energy efficiency by 20.5% and 15.0%, respectively.
Event Type
Research Manuscript
TimeThursday, June 271:30pm - 1:45pm PDT
Location3008, 3rd Floor
Embedded Systems
Embedded Memory and Storage Systems