Presentation
G-PASTA: GPU Accelerated Partitioning Algorithm for Static Timing Analysis
DescriptionStatic timing analysis (STA) is an important stage in the modern EDA design flow. But STA becomes timing-consuming with the growth of modern circuit size. Recent research has leveraged task dependency graph (TDG) parallelism to accelerate STA. Despite the speedup through TDG parallelism, the performance can be further enhanced by reducing the scheduling cost. A common solution for reducing scheduling cost is TDG partitioning. However, the runtime of existing TDG partitioning algorithms grows rapidly as the TDG size enlarges. Also, TDG partitioning is frequently invoked during STA process. This make TDG partitioning runtime adds up to a significant portion of the entire STA runtime. As a result, it is important to optimize the runtime performance of TDG partitioning.
In this paper, we propose G-PASTA, a GPU-accelerated TDG partitioning algorithm by harnessing the computation power of modern GPU architectures. We evaluate the performance of G-PASTA on a set of TDGs from large designs. Compared to the state-of-the-art TDG partitioner, G-PASTA is up to 41.8× faster, while improving TDG runtime by 2×.
In this paper, we propose G-PASTA, a GPU-accelerated TDG partitioning algorithm by harnessing the computation power of modern GPU architectures. We evaluate the performance of G-PASTA on a set of TDGs from large designs. Compared to the state-of-the-art TDG partitioner, G-PASTA is up to 41.8× faster, while improving TDG runtime by 2×.
Event Type
Research Manuscript
TimeTuesday, June 2511:15am - 11:30am PDT
Location3008, 3rd Floor
EDA
Timing and Power Analysis and Optimization