Presentation
ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model
DescriptionThe memory wall is a growing issue in modern comput-
ing systems due to the disparity between device computing
power and data communication speed. To alleviate mem-
ory wall, Compute Express Link (CXL) is proposed to cre-
ate a shared and coherent memory space between the host
and device, offering opportunities to use device DRAM as
cache and device memory as primary storage for memory-
intensive tasks. However, challenges arise when utilizing
device DRAM as cache, including high cache miss penalties
caused by data access granularity mismatches and ineffi-
cient hardware cache management mechanisms. To tackle
these issues, we propose Smart DRAM-Caching, an efficient
framework that employs Gaussian Mixture Model (GMM)
for intelligent caching and eviction on hardware. Compared
with traditional cache replacement strategies LRU, our on-
board measurements reveal that a ?% increase in cache hit
rate can result in a ?% reduction in average device memory
access latency. Compared with learning-based methods like
LSTM, our approach achieves ?× speedup with less hardware
resource consumption.
ing systems due to the disparity between device computing
power and data communication speed. To alleviate mem-
ory wall, Compute Express Link (CXL) is proposed to cre-
ate a shared and coherent memory space between the host
and device, offering opportunities to use device DRAM as
cache and device memory as primary storage for memory-
intensive tasks. However, challenges arise when utilizing
device DRAM as cache, including high cache miss penalties
caused by data access granularity mismatches and ineffi-
cient hardware cache management mechanisms. To tackle
these issues, we propose Smart DRAM-Caching, an efficient
framework that employs Gaussian Mixture Model (GMM)
for intelligent caching and eviction on hardware. Compared
with traditional cache replacement strategies LRU, our on-
board measurements reveal that a ?% increase in cache hit
rate can result in a ?% reduction in average device memory
access latency. Compared with learning-based methods like
LSTM, our approach achieves ?× speedup with less hardware
resource consumption.
Event Type
Research Manuscript
TimeThursday, June 272:45pm - 3:00pm PDT
Location3003, 3rd Floor
Design
In-memory and Near-memory Computing Circuits