Presentation
PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture
DescriptionModern SSD firmware is continuously optimized for higher parallelism to match the growing frontend PCIe bandwidth with more backend flash channels. Although a multi-core microprocessor is typically adopted to concurrently process independent NVMe requests from multiple NVMe queues, the existing one-to-many thread-request mapping model with each thread serving one or more incoming I/O requests has poor scalability due to severe lock contention problem, especially in cache management.
In this paper, we first conduct preliminary experiments on an open-channel NVMe SSD to exhibit the lock contention problem in the one-to-many thread-request mapping model. When a thread locks a cache line and is waiting for a long-latency flash read to update this cache line, subsequent tasks on other threads that require the same cache line are all blocked to guarantee correctness. To mitigate this, we propose PipeSSD, a lock-free pipeline-based SSD firmware design with a many-to-one thread-request mapping model that assigns multiple threads to serve different stages of each I/O request in a pipelined way. It is worth noting that PipeSSD only performs cache updates in the last pipeline stage to eliminate dependency loops in the pipeline while maintaining a pilot for each cache line in the beginning pipeline stage to indicate the cache line status. With a multi-core architecture, different pipeline stages are processed on different cores communicated via several FIFO queues, which can ensure the processing sequence and data consistency without any cache line locks. We implement PipeSSD on real hardware and evaluate its performance on a multi-core NVMe SSD prototype. The evaluation results show that on an 8-core system, PipeSSD has a significant throughput improvement compared to the state-of-the-art multi-core SSD firmware.
In this paper, we first conduct preliminary experiments on an open-channel NVMe SSD to exhibit the lock contention problem in the one-to-many thread-request mapping model. When a thread locks a cache line and is waiting for a long-latency flash read to update this cache line, subsequent tasks on other threads that require the same cache line are all blocked to guarantee correctness. To mitigate this, we propose PipeSSD, a lock-free pipeline-based SSD firmware design with a many-to-one thread-request mapping model that assigns multiple threads to serve different stages of each I/O request in a pipelined way. It is worth noting that PipeSSD only performs cache updates in the last pipeline stage to eliminate dependency loops in the pipeline while maintaining a pilot for each cache line in the beginning pipeline stage to indicate the cache line status. With a multi-core architecture, different pipeline stages are processed on different cores communicated via several FIFO queues, which can ensure the processing sequence and data consistency without any cache line locks. We implement PipeSSD on real hardware and evaluate its performance on a multi-core NVMe SSD prototype. The evaluation results show that on an 8-core system, PipeSSD has a significant throughput improvement compared to the state-of-the-art multi-core SSD firmware.
Event Type
Research Manuscript
TimeThursday, June 272:30pm - 2:45pm PDT
Location3008, 3rd Floor
Embedded Systems
Embedded Memory and Storage Systems