Presentation
SSH-SoC: Safety and Security in Heterogeneous Open System-on-Chip Platforms
DescriptionThe diminishing returns of technology scaling on performance have paved the way for innovation in computer architecture, shifting towards heterogeneous, domain-specific architectures. Modern systems incorporate domain-specific accelerators and specialized system components (buses, network-on-chip, peripherals, sensors, etc..) to efficiently manage complex and computationally demanding workloads.
A widely adopted approach to reduce the System-on-Chip (SoC) design complexity involves a hierarchical strategy that differentiates the system design efforts for the components of the heterogeneous architecture. This encompasses: (i) expensive in-house RTL development for critical modules, (ii) leveraging the most recent high-level synthesis (HLS) tools, and/or (iii) outsourcing highly specialized third-party intellectual property (IP) modules to reduce costs and development time.
Despite its advantages, such diversified design methodology exacerbates the challenge of system integration. Moreover, recent studies have demonstrated how careless system integration can lead to dangerous conditions, impacting the security, safety, and performance of the system. This can result from a combination of factors, including development bugs, lack of specifications, superficial verifications of IP components' behavior at the system level, and a scarcity of mechanisms supporting safe and secure system execution.
Addressing these challenges requires innovative approaches in the design and verification process, especially when dealing with the stringent safety and security requirements of mission-critical systems. The research community can play a disruptive role in overcoming these challenges. The availability of the complete codebase of multiple mature open hardware architectures and reconfigurable platforms represents an unprecedented opportunity for the development, testing, and native integration of novel mechanisms, tools, and analysis supporting security, safety, and performance efficiency for the development of the next-generation of systems.
This workshop welcomes work-in-progress contributions and innovative directions aimed at addressing challenges and profit from the opportunities provided by open hardware designs and architectures for the development of next-generation heterogeneous SoCs. The topics for the workshop include, but are not restricted to:
Security verification for hardware designs and system architectures
Architectural aspects of secure system integration
Secure system integration of third-party hardware components
Automated firmware generation supporting secure system execution
Security aspects of reconfigurable designs
Time-predictable system execution in open-hardware designs
Performance analysis, timing analysis, and worst-case analysis supporting
time-predictable system execution and/or communications in open-hardware designs
Automated firmware generation supporting time-predictable execution
Fault tolerance and execution in harsh conditions leveraging open-hardware designs
System architectures and methodologies supporting energy efficient/performant system execution in open-hardware designs
Hardware/software co-design, co-integration and co-verification of open-source processors, accelerators, and components
Open architectures for reconfigurable platforms and open CAD tools
Tools and analysis for open FPGAs and reconfigurable platforms
A widely adopted approach to reduce the System-on-Chip (SoC) design complexity involves a hierarchical strategy that differentiates the system design efforts for the components of the heterogeneous architecture. This encompasses: (i) expensive in-house RTL development for critical modules, (ii) leveraging the most recent high-level synthesis (HLS) tools, and/or (iii) outsourcing highly specialized third-party intellectual property (IP) modules to reduce costs and development time.
Despite its advantages, such diversified design methodology exacerbates the challenge of system integration. Moreover, recent studies have demonstrated how careless system integration can lead to dangerous conditions, impacting the security, safety, and performance of the system. This can result from a combination of factors, including development bugs, lack of specifications, superficial verifications of IP components' behavior at the system level, and a scarcity of mechanisms supporting safe and secure system execution.
Addressing these challenges requires innovative approaches in the design and verification process, especially when dealing with the stringent safety and security requirements of mission-critical systems. The research community can play a disruptive role in overcoming these challenges. The availability of the complete codebase of multiple mature open hardware architectures and reconfigurable platforms represents an unprecedented opportunity for the development, testing, and native integration of novel mechanisms, tools, and analysis supporting security, safety, and performance efficiency for the development of the next-generation of systems.
This workshop welcomes work-in-progress contributions and innovative directions aimed at addressing challenges and profit from the opportunities provided by open hardware designs and architectures for the development of next-generation heterogeneous SoCs. The topics for the workshop include, but are not restricted to:
Security verification for hardware designs and system architectures
Architectural aspects of secure system integration
Secure system integration of third-party hardware components
Automated firmware generation supporting secure system execution
Security aspects of reconfigurable designs
Time-predictable system execution in open-hardware designs
Performance analysis, timing analysis, and worst-case analysis supporting
time-predictable system execution and/or communications in open-hardware designs
Automated firmware generation supporting time-predictable execution
Fault tolerance and execution in harsh conditions leveraging open-hardware designs
System architectures and methodologies supporting energy efficient/performant system execution in open-hardware designs
Hardware/software co-design, co-integration and co-verification of open-source processors, accelerators, and components
Open architectures for reconfigurable platforms and open CAD tools
Tools and analysis for open FPGAs and reconfigurable platforms
Event Type
Workshop
TimeSunday, June 238:00am - 5:00pm PDT
Location3002, 3rd Floor
Security