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Presenter

Jiliang Zhang
Hunan University
Presentations
Research Manuscript
S2RAM PUF: An Ultra-low Power Subthreshold SRAM PUF with Zero Bit Error Rate
Security
Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
SPECRUN: The Danger of Speculative Runahead Execution in Processors
Security
Embedded and Cross-Layer Security
Research Manuscript
An NTT/INTT Accelerator with Ultra-High Throughput and Area Efficiency for FHE
Security
Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency
Security
Hardware Security: Primitives, Architecture, Design & Test