Presentation
An NTT/INTT Accelerator with Ultra-High Throughput and Area Efficiency for FHE
SessionHardware Security Primitives
DescriptionAs a core arithmetic operation and security guarantee of Fully Homomorphic Encryption (FHE), Number Theoretic Transform (NTT) of a large degree is the primary source of computational and time overhead. In this paper, we propose a scalable and conflict-free memory mapping algorithm that breaks the memory bound and releases a large amount of on-chip resources. A flexible and no-stall hardware/software pipeline architecture is designed to boost the throughput of NTT/INTT of $N=2^{16}$ to over 48,543 operations per second with area efficiency, which 4× and 10× speed up the FPGA-based (HPCA'23) and GPU-based (HPCA'23) schemes.
Event Type
Research Manuscript
TimeWednesday, June 264:30pm - 4:45pm PDT
Location3012, 3rd Floor
Security
Hardware Security: Primitives, Architecture, Design & Test