Presentation
Automatic Layout Symmetry Annotation via Graph Node Embeddings
DescriptionThe identification of layout constraints in analog circuits such as symmetry, matching, etc. has become a crucial task to meet more and more aggressive design specifications, especially in new process nodes where parasitic effects can have a severe impact on circuit performance and lifetime. However, the manual annotation of such constraints requires design expertise and is a challenging and error prone task. In this paper, we propose an unsupervised node embedding method on circuit netlist graph to capture topological similarities between nodes. We evaluate our method on open-source and in-house analog circuit designs to validate the ability of this new approach to identify symmetry constraints. Compared to other solutions based on machine learning (ML) techniques recently proposed in the literature that rely on annotated netlists datasets, this unsupervised solution does not need any prior knowledge usually extracted during computationally expensive machine learning phase.
Event Type
Back-End Design
TimeMonday, June 242:42pm - 3:00pm PDT
Location2008, 2nd Floor
Back-End Design
Design
Engineering Tracks