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Session

Back-End Design: Exploring Alternative Corridors for optimal routes
Session Chair
Patricia Fong
Marvell Semiconductor
DescriptionFind your inner Nemo! Explore multiple pathways to getting around the barriers in floorplanning, be it memories. cutlines or using the symmetry of the edges. Use AI to assist your route plan.
Event TypeBack-End Design
TimeMonday, June 241:30pm - 3:00pm PDT
Location2008, 2nd Floor
Topics
Back-End Design
Design
Engineering Tracks
Presentations
1:30pm - 1:48pm PDTA Novel Solution for Fast and Efficient Custom Bus Routing with User-defined Reference Wire and Combination of Segmented Bus Option
Presenters
SUNGSIK PARK
Keunbong Lee
1:48pm - 2:06pm PDTMemory IO Block Routing Optimization using Semi-Automation of Single Trunk Steiner Tree Routing
Presenters
Seyong Ahn
Hyeyoun Kim
Kwangok Jeong
Jungyun Choi
2:06pm - 2:24pm PDTA New Frontier for Floorplanning with AI
Presenters
Pinkesh Shah
Alpesh Kothari
Raghu Ram Gude
2:24pm - 2:42pm PDTA Systematic Approach to 3D Cutline Exploration and Benchmarking
Presenters
Chung-Ching Peng
Justin Aguilar
Kurt Chu
CH Yang
Zih-Nan Tseng
Aaron Liou
Wei Zhou
Bryant Chang
Vivek Rajan
Pinhong Chen
Jags Jayachandran
Naresh Mummidivarapu
Yashodhara Tarey
Kumar Subramani
2:42pm - 3:00pm PDTAutomatic Layout Symmetry Annotation via Graph Node Embeddings
Presenters
Jerome Lescot
Francois Lemery