Presentation
A novel formal verification technique to System verification using contract refinement
DescriptionCurrently, formal verification techniques succumb when it comes to the verification of system-level behavior. Only a handful of properties are converged by state-of-the-art SMT solvers. Moreover, the current state-of-the-art frameworks do not address the formal verification aspects as the scale of the design increases beyond the component level, they are: Consistency (if the design is over-constrained), completeness( The set of properties considered are exhaustive) and correctness(if the properties describe the correct behavior). In our solution to system-level verification, we address all of these concerns in our proposed approach. We show in our experiments all the properties either converge with a better bound or show higher bounds as compared to the legacy techniques. This leads us to say with confidence that our solution works well for subsystem-level design verification. While we submit this work, experiments are still ongoing to check the viability of this solution if the designs are further scaled up.
Event Type
Front-End Design
TimeMonday, June 242:45pm - 3:00pm PDT
Location2010, 2nd Floor
Design
Engineering Tracks
Front-End Design