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Session

Front-End Design: Static and Formal Verification: Pillars of Modern Design Assurance
Session Chair
Puneet Anand
Qualcomm
DescriptionStatic and formal based flows/solutions provide bottom-up verification approach, this helps to find certain class of bugs in the shortest time and help manage efficient distribution of load across all verification technologies. In this session, presenters will share their experiences on applications like data path validation, formal verification, and CDC (clock domain crossing) verification.
Event TypeFront-End Design
TimeMonday, June 241:30pm - 3:00pm PDT
Location2010, 2nd Floor
Topics
Design
Engineering Tracks
Front-End Design
Presentations
1:30pm - 1:45pm PDTEnhancing Formal Equivalence for Datapath Algorithms: A Proof Strategy with Intermediate Modeling to Address Structural Differences in Implementations
Presenters
Suraj Kamble
Swaresh Phadke
Disha Puri
Aarti Gupta
1:45pm - 2:00pm PDTLeveraging Formal Verification to Create, Reproduce, Verify Design Scenarios from Simulation Wave-dump
Presenters
Ujjwal Talati
Saikiran Ashwini
Aman Chauhan
Viraj Rawal
Nivin George
2:00pm - 2:15pm PDTFormal CDC Glitch Check - Advanced Sign Off Solution
Presenters
Noam Eshel Goldman
Liad Nehama
Vikas Sachdeva
Polina Pashayev
2:15pm - 2:30pm PDTBreaking the Formal Convergence Barriers of a Floating-Point Dot-Product Block for AI/ML Accelerators
Presenters
Satyabrata Sarangi
Neelabja Dutta
Sai Ma
Ashish Kapoor
Reily Jacoby
Adrian Lewis
Rohan Mallya
Eda Sahin
2:30pm - 2:45pm PDTSecuring Safe Customization of RISC-V Cores via Rigorous Sequential RTL Comparison
Presenters
Nicolae Tusinschi
Laurent Arditi
2:45pm - 3:00pm PDTA novel formal verification technique to System verification using contract refinement
Presenters
surinder sood
Nirmal Jose
Scott Meeth