Presentation
Open Compute Platform(OCP) ready Hardware Accelerated CXL Memory Compression IP for Data Center Applications
SessionLeading edge digital IP
DescriptionThe Compute Express Link (CXL) 3.1 specification introduces hardware support for cache coherence, facilitating efficient access to shared memory pools in data centers, crucial for addressing the growing memory demand from AI applications. However, challenges in Cost, Efficiency, and Sustainability impede the widespread deployment of CXL platforms at Hyperscale. In response, Meta and Google have unveiled a hardware-compressed CXL memory tier within the Open Compute Project (OCP) / Composable Memory System (CMS) framework, aiming to achieve sustainable and responsible data center operations across diverse compute platforms and memory technologies.
We present DenseMem, an OCP-compliant Memory Compression IP, the hardware-accelerated solution enhances effective capacity by 2-4x with sub 10ns latency at full bandwidth. Leveraging a novel cache line granularity compression algorithm, DenseMem is an area and power-efficient IP block compatible with the latest process nodes. Currently available for evaluation, DenseMem is scheduled for production deployment in mid-2024. It seamlessly integrates into CXL Type 3 device Systems-on-Chip (SoCs) between the CXL controller and memory controller logic blocks, supporting AXI4 and CHI specifications. The lightweight firmware of DenseMem facilitates communication via CXL.mem commands, exposing compressed memory regions for easy integration into existing Linux stacks, applications, and fabric management software.
We present DenseMem, an OCP-compliant Memory Compression IP, the hardware-accelerated solution enhances effective capacity by 2-4x with sub 10ns latency at full bandwidth. Leveraging a novel cache line granularity compression algorithm, DenseMem is an area and power-efficient IP block compatible with the latest process nodes. Currently available for evaluation, DenseMem is scheduled for production deployment in mid-2024. It seamlessly integrates into CXL Type 3 device Systems-on-Chip (SoCs) between the CXL controller and memory controller logic blocks, supporting AXI4 and CHI specifications. The lightweight firmware of DenseMem facilitates communication via CXL.mem commands, exposing compressed memory regions for easy integration into existing Linux stacks, applications, and fabric management software.
Presenter
Event Type
IP
TimeMonday, June 242:45pm - 3:00pm PDT
Location2012, 2nd Floor
Engineering Tracks
IP