Session

DescriptionDigital IP design has to improve rapidly to catch up with the speed and performance requirements for massive compute intensive applications in the AI era. IP designers are exhausting every possible combination to improve power, performance and area efficiency of digital design. In this section, we talk about algorithmic changes that double the throughput of an Ethernet switch, a fast calibration method for PHYs, an FPGA based hardware accelerator, AI based technology library selection to optimize the PPA, arbiter logic for high performing systems and a highly efficient CXL memory compression design for data center applications.