Presentation
Accelerating Timing Closure for Network on Chips (NoCs) using Physical Awareness
DescriptionWith the rapidly rising number of computing and peripheral building blocks in modern System-on-chip (SoC) development quickly being in the 100s, the interconnect between these blocks can become the long pole for timing analysis and significantly contribute to power consumption. Networks-on-Chips (NoCs) have emerged as the critical solution for on-chip communication and have seen a rapid rise in protocol complexity for coherent and non-coherent designs, and flows for automated RTL generation of configurable NoC IP from high-level topology descriptions have emerged.
With the transport delay increasingly dominated by RC wiring delay, changes in the NoC topology caused by difficulties in timing closure during the Place and Route (P&R) phase can add significant project delays.
This presentation will outline a flow and methodology that uses earlier, abstracted technology information to efficiently guide the development of NoCs using .lef/.def based import of floorplan information to inform NoC-topology development and export constraint and placement information as guidance to standard digital implementation flows to avoid late surprises in timing closure.
With the transport delay increasingly dominated by RC wiring delay, changes in the NoC topology caused by difficulties in timing closure during the Place and Route (P&R) phase can add significant project delays.
This presentation will outline a flow and methodology that uses earlier, abstracted technology information to efficiently guide the development of NoCs using .lef/.def based import of floorplan information to inform NoC-topology development and export constraint and placement information as guidance to standard digital implementation flows to avoid late surprises in timing closure.
Event Type
IP
TimeWednesday, June 262:24pm - 2:42pm PDT
Location2012, 2nd Floor
Engineering Tracks
IP