Presentation
A New Design Verification Era as Open-Source Upends the Status Quo
DescriptionRISC-V and a growing open-source ecosystem have moved from hype to reality. Consequently, the semiconductor industry is at an inflection point as architectural paradigms require early power and performance metrics, creating demand for new design, verification and validation technologies and methodologies.
Engineers now have the ability to design a specific rather than generic open-source instruction set easily customizable to an application in a vertical market. It's an era where RISC-V starts are not just starts but used in volume production.
The status quo has been upended and with it a challenge with a new open-source ecosystem versus the trust of a traditional, well-established and rich ecosystem. The new open-source instruction set and software don't have legacy, experience and domain knowledge sharing, particularly software validation's usage and experience.
It could also become an exciting era for design verification as it becomes the chief enabler for the new ecosystem and architecture, especially hardware-assisted verification that can serve as a risk mitigation tool.
A panel of design and verification users and experts, all of whom have studied the open-source ecosystem and its requirements and deficiencies, will be part of the DAC Pavilion Panel. DAC attendees are invited to listen in as they discuss where emphasis should be placed for the next-generation design verification flow. Audience participation will be encouraged.
Engineers now have the ability to design a specific rather than generic open-source instruction set easily customizable to an application in a vertical market. It's an era where RISC-V starts are not just starts but used in volume production.
The status quo has been upended and with it a challenge with a new open-source ecosystem versus the trust of a traditional, well-established and rich ecosystem. The new open-source instruction set and software don't have legacy, experience and domain knowledge sharing, particularly software validation's usage and experience.
It could also become an exciting era for design verification as it becomes the chief enabler for the new ecosystem and architecture, especially hardware-assisted verification that can serve as a risk mitigation tool.
A panel of design and verification users and experts, all of whom have studied the open-source ecosystem and its requirements and deficiencies, will be part of the DAC Pavilion Panel. DAC attendees are invited to listen in as they discuss where emphasis should be placed for the next-generation design verification flow. Audience participation will be encouraged.
Moderator
Event Type
DAC Pavilion Panel
TimeMonday, June 242:00pm - 2:45pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Design