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Organization

Siemens
Contributors
Mohamed Alimam
Ben Allen
Hicham Anbar
Mohammad Saif Ansari
Zvart Askanazyan
Mohamed Atoua
Manish Bhati
Jean-Marie Brunet
Sunsoo Byun
Vijay Chobisa
JeongGuk Choi
Sung-Soon Choi
Joe Davis
Antonio de la Serna
Keerthikumara Devarajegowda
Amit Dey
Parul Dohare
Jeff Dyck
Jeff Dyck
Mohammed Fahad
Raghu Gude
Sanchita Gupta
Tony Hemmelgarn
Nermeen Hossam
Jin Hou
Lih-Jen Hou
Mahima Jain
Sulabh Khare
Lars Kishchuk
Alpesh Kothari
Ajay Kumar
Manish Kumar
Sachin Kumar
Gurpreet Lamba
Gurpreet Singh Lamba
Jaejun Lee
Sungyoun Lee
Eric Mammi
Tony Mastroianni
Fillaud Matthieu
Christian Miles
Anil Mishra
Fouad Mkalech
Abdul Moyeen
Anish Padhi
Divya Parihar
Bhupesh Prajapat
Vani Priya
Siddharth Ravikumar
Mary Rayburn
REETIKA REETIKA
Juan Rey
Dave Rich
Ahmed Saleh
Rahul Seth
Kesmat Shahin
Heba Sharaf
Austin Shirley
Smitha Shivaji Kamathi
GAZAL SINGLA
GAZAL SINGLA
Sasa Stamenkovic
Esraa Swilliam
Pratik Talekar
Wei-Lii Tan
Vijay Tayal
Pradeep Thiagarajan
Jeff Wilson
Session Chairs
Dave Rich
Presentations
DAC Pavilion Panel
A New Design Verification Era as Open-Source Upends the Status Quo
Design
Back-End Design
A New Frontier for Floorplanning with AI
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
A Novel methodology for re-simulation of block vectors helping validate Power Optimization QoR 20x faster
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Accelerating IO Liberty Generation through ML based Solution
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
AI-Assisted Design Optimization for Extensive Design Spaces: Handling 260,000+ Combinations
Back-End Design
Embedded Systems
Front-End Design
IP
IP
AI-based High Sigma Verification Methodology for Multiple PVT Corners
Engineering Tracks
IP
Front-End Design
AI-Powered High-Sigma Automated Full Library Verification Methodology for Standard Cells
AI
Design
Engineering Tracks
Front-End Design
Engineering Track Poster
An Automated Solution for Streamlining Qualifications of Connectivity and DRC Across Diverse 3DIC Packaging Technologies
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
An efficient QA methodology for SRAM libraries
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Autonomous Power Sequence validation solution for I/O using Solido Design Environment
Back-End Design
Embedded Systems
Front-End Design
IP
DAC Pavilion Panel
Best of Both Worlds: Bridging the Gaps in Engineering Software for Semiconductors and Systems
DAC Pavilion Panel
Blackout – Managing kW Power Budgets
Design
Engineering Track Poster
Bus Delay Skew Minimization for High Bandwidth Memory Designs
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Critical corners selection for standard cells LVF characterization using AI
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Design Automation Advancement in the Analog Domain
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Empowering CDC analysis methodology with root cause analysis
Back-End Design
Embedded Systems
Front-End Design
IP
Exhibitor Forum
Enabling a new era of Software Shift Left with Veloce CS
IP
Evaluating power, performance, and area for standard cell libraries from different IP providers
Engineering Tracks
IP
Engineering Track Poster
High Coverage QA for Process Variability Compensation in LVS Rule Deck
Back-End Design
Embedded Systems
Front-End Design
IP
Exhibitor Forum
How AI is changing every aspect of EDA, starting from transistor-level simulation
EDA
Engineering Track Poster
Implementing World's First Fully Integrated SoC Solution For Direct-To-Satellite IoT Connectivity
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Interfacing High-Voltages Directly to Low Power CMOS Process Die for RF, MEMs and Analog Applications
Engineering Tracks
IP
Research Manuscript
MCU-Wide Timing Side Channels and Their Detection
Security
Hardware Security: Primitives, Architecture, Design & Test
Engineering Track Poster
Microsoft's Comprehensive IP Handoff Flow
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Overcoming the Growing Challenge of IR Drop by Effective Power Grid Enhancement during Chip Finishing
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Parasitic Leakage Detection in Layout Design
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Peak Power Optimization using Active Datapath Operator Profiling
Back-End Design
Embedded Systems
Front-End Design
IP
Research Panel
Power Your Future: Investments for the Chip Design Workforce and Research
EDA
Back-End Design
Pruning Netlist: A Smarter Approach to Efficient and Reliable Circuit Characterization
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Rapid Retargeting of Formal Connectivity Verification of AI FPGA Systems
Back-End Design
Embedded Systems
Front-End Design
IP
Work-in-Progress Poster
Reset Domain Crossing Design Verification Closure using Advanced Data Analytics Techniques
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Engineering Track Poster
Resolving the seed promotion due to device layers derivation
Back-End Design
Embedded Systems
Front-End Design
IP
IP
Samsung's IP QA methodology using Solido Crosscheck
Engineering Tracks
IP
Engineering Track Poster
Shift-left methodology to identify invalid voltage level shifts & validate signal pins' P/G association in IPs/Block's UPF & .LIB views using PERC's static-voltage tracing mechanism
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Solving the antenna debug challenge in physical design verification
Back-End Design
Embedded Systems
Front-End Design
IP
Exhibitor Forum
Taking 3D IC Heterogeneous Integration Mainstream
Engineering Track Poster
The Designer's Superpower! Early Circuit Verification with Calibre nmLVS Recon
Back-End Design
Embedded Systems
Front-End Design
IP
TechTalk
The Evolution of the Digital Twin in Semiconductor design, and the central role AI plays
AI
Design
Front-End Design
What is the Future of Design Verification? UVM, PSS, Formal, VIP, AI & Beyond
AI
Design
Engineering Tracks
Front-End Design
Sessions
Front-End Design
Advanced Verification
Design
Engineering Tracks
Front-End Design