Presentation
Instruction Sequence Generation using Reinforcement Learning for Software-Based Self-Test of Processor Cores
DescriptionWith the rise of faulty chips post-deployment, efficient in-field testing becomes crucial. This paper introduces a novel method for generating software-based self-test (SBST) programs for processor cores using reinforcement learning, employing toggle coverage as a proxy metric. Our approach, which builds test programs incrementally, was tested on two types of RISC-V cores. It outperformed random generation, achieving over 80% toggle coverage for 200 instructions. When evaluated with the stuck-at-fault model, it showed a substantial improvement in fault coverage, enhancing the coverage achieved through random methods by 1.7 times in out-of-order cores, thus demonstrating its robustness in in-field testing.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security