Session Full Program · Contributors · Organizations · Search Program · Flagged · Happening NowMore…Search ProgramFlaggedHappening NowWork-in-Progress Poster: Wednesday Work-in-Progress PostersEvent TypeWork-in-Progress PosterTimeWednesday, June 265:00pm - 6:00pm PDTLocationLevel 2 LobbyTopicsAIAutonomous SystemsCloudDesignEDAEmbedded SystemsIPSecurityPresentationsRetract: Logarithmic-Depth Reconstruction of Continuous Controlled-NOT Logic BlockAuthorsEnhyeok JangSungwoo AhnWon Woo RoPINN-based Compact Model for On-chip Silicon Photonic DevicesAuthorsYuxiang FuYinyi LiuJiaxu ZhangTianshu HouNgai WongJiang XuHDFusion: Hierarchical Data Fusion for Robust Deep Tissue SensingAuthorsTailai LiheBegum KasapKourosh ValiSoheil GhiasiCIMAP: A CIM Crossbar Array Data Mapping Methodology for Unstructured Sparse Convolutional Neural NetworksAuthorsYan-Lin HungBing-Han LiuZun-Sheng WuBo-Cheng LaiShyh-Jye JouA DRAM-based PIM Architecture for Accelerated and Energy-Efficient Execution of TransformersAuthorsGian SinghSarma VrudhulaCircuit Transformer: End-to-end Logic Synthesis by Predicting the Next GateAuthorsXihan LiXing LiLei ChenXing ZhangMingxuan YuanJun WangEffiPipe: Towards Energy-Efficient Large-scale Model Training on Commodity GPUsAuthorsZijie TianShuo WangYuhao ZhangYouyou LuJiwu ShuRobustState: Boosting Fidelity of Quantum State Preparation via Noise-Aware Variational TrainingAuthorsHanrui WangYilian LiuPengyu LiuJiaqi GuZirui LiZhiding LiangJinglei ChengYongshan DingXuehai QianYiyu ShiFrederic ChongSong HanEfficient Prediction of SRAM Read Access Time and Yield via Neural Network Leveraging Transfer Learning and Transformer ModelsAuthorsSungho ParkJaehyeon MoonGiseok KimDohyung KimSeong-Ook JungBumsub HamHanwool JeongH4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR ApplicationsAuthorsYiwei ZhaoZiyun LiWin-San KhwaXiaoyu SunSai Qian ZhangSyed Shakib SarwarKleber StangherlinYi-Lun LuJorge GomezJae-sun SeoPhillip GibbonsBarbara De SalvoChiao LiuAccelerating DNN Execution via Weight and Data Adaptive N:M PruningAuthorsSai Qian ZhangThierry TambeGu-Yeon WeiDavid BrooksQPulse: Ansatz Design Analysis and Advantages of Parameterized Quantum PulsesAuthorsZhiding LiangJinglei ChengZhixin SongHang RenRui YangHanrui WangKecheng LiuPeter KoggeTongyang LiYongshan DingYiyu ShiDB-Hunter: Interactive-Guided Differential Testing for FPGA Simulation DebuggerAuthorsShikai GuoXiaoyu WangZhihao XuXiaochen LiHe JiangAutomated Generation of OoO ASIP from ISA Documents via Nano-Operator AbstractionAuthorsChongxiao LiPengwei JinTianyun MaShuyao ChengYongwei ZhaoGuanglin XuZidong DuRui ZhangXiaqing LiYuanbo WenXing HuQi GuoAgile Discovery of Efficient Real-Time Systems-on-Chips in the Heterogeneous EraAuthorsSubhankar PalAporva AmarnathBehzad BoroujerdianAugusto VegaAlper BuyuktosunogluJohn-David WellmanVijay Janapa ReddiPradip BoseHardware PDE Solvers Using Dynamic Stochastic ComputingAuthorsHongqiao ZhangZhengkun YuJie HanSiting LiuCirSTAG: Circuit Stability Analysis via Graph Neural NetworksAuthorsWuxinlin ChengYihang YuanChenhui DengAli AghdaeiZhiru ZhangZhuo FengA New Iterative Method with Krylov Subspace Recycling for Efficient Periodic AC and Noise AnalysisAuthorsLingyun OuyangChao JinQuan ChenSeGen: Automatic Topology Generator of Sequencing ElementAuthorsKyounghun KangWanyeong JungShared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-MemoryAuthorsAhmed MamdouhHaoran GengMichael NiemierX. Sharon HuDayane ReisTACPlace: Ultrafast Thermal-Aware Chiplet Placement under Multi-Power Mode Using Feasibility SeekingAuthorsShan YuHaiyang LiuXinming WeiGuojie LuoConfidential Computing with Heterogeneous Devices at Cloud-ScaleAuthorsAritra DharSupraja SridharaShweta ShindeSrdjan CapkunRenzo AndriEliminate control divergence in SpMV via in-SRAM reductionAuthorsZhang DunboJia ChaoyangLi ShenLu KaiAnalysis of 64-bit Parallel Prefix Adders and 32-bit Matrix Multiply Units Designed with 7-nm CNFETAuthorsChenlin ShiShinobu MiwaTongxin YangRyota ShioyaHayato YamakiHiroki HondaImprovements to Delay-driven LUT MappingAuthorsAlessandro Tempia CalvinoGiovanni De MicheliAlan MishchenkoRobert BraytonDRL-based Voltage Optimization for Multiple Droplet Routing in DMFBsAuthorsTomohisa KawakamiHiroki NishikawaHiroyuki TomiyamaShigeru YamashitaAccelerating Large-scale Sparse LU Factorization for RF Circuit SimulationAuthorsGuofeng FengHongyu WangZhuoqiang GuoMingzhen LiTong ZhaoZhou JinWeile JiaGuangming TanNinghui SunAccelerating Range-Joins for Big Data Genomic Variant Annotation on HBM-enabled FPGAsAuthorsAman SinhaShih-Chen LoBo-Cheng LaiSVDE: Serverless System for Low-Latency Video Analytic Queries Using Tree-based RegressionAuthorsPingyi HuoTheodoros MichailidisYi ZhengPrapti PanigrahiKiwan MaengJISHEN ZHAOVijaykrishnan NarayananA verification plan to assess the quality of mobile telephony in BrazilAuthorsJoel OliveiraMarcio KreutzxPMEM: A Design of Byte-Addressable Persistent Memory with Compute Express Link for Advanced Data Center ApplicationsAuthorsFei XueXun ChenMengting LuDengcai XuFred AuHao DingKun WangKai TaoFeng ZhuFengguo ZuoYubing WangXiaofeng ZhouBin HouXin XuWei LiShijie FanLiang ZhongJing LvXiping JiangShu LiKnowledge is Power: A Knowledge-Guided Oracle-Less Attack on Logic LockingAuthorsAbir Ahsan AkibYuntao LiuAnkur SrivastavaAn instant leafcell layout auto-generator for area compact memory design automationAuthorsWonjoon JoGiseok KimSungho ParkSeong-Ook JungHanwool JeongPCBench: A Dataset for Printed Circuit Board RoutingAuthorsYoubiao HeJacob FriedenHebi LiRoba AbbajabalGe LuoForrest Sheng BaoA Novel Approach: Applying Fractional Factorial Design Methodology to Stress-Map, Experimental Study for Stress-Induced Failure (Bug), and Stress Coverage Assessment in Post-Silicon Validation ProcessAuthorslay wai kongGlenn Benton GibbsGL0AM: GPU Logic Simulation Using 0-Delay and Re-simulation Acceleration MethodAuthorsYanqing ZhangHaoxing RenBrucek KhailanyWorst Case Response Time Analysis for Completely Fair Scheduling in Linux SystemsAuthorsKyonghwan YoonEunJin JeongWoosuk KangJonghyun ChoeSoonhoi HaReS-CIM: ReRAM-cached SRAM Compute-in-Memory Architecture with a Differential Sensing Scheme Enabling Intra-Macro Weight LoadingAuthorsXiaomeng WANGJingyu HEJiakun ZHENGFengshi TIANFengbin TUTim Kwang-Ting CHENGChi-Ying TSUIFOTA-Quant: FPGA-Oriented Token Adaptive Quantization Framework for the Acceleration of LLMsAuthorsXuan ShenZhaoyang HanPeiyan DongYanyue XieZhenglun KongZhengang LiYanzhi WangMiriam LeeserSPulseGen: Succinct pulse generator architecture maximizing gate fidelity for superconducting quantum computersAuthorsRyosuke MatsuoKazuhisa OgawaHidehisa ShiomiMakoto NegoroTakefumi MiyoshiMichihiro ShintaniHiromitsu AwanoTakashi SatoJun ShiomiMAM-CIM: Data Resilience Scheduling Based Multilevel Analog Memory for Near Sensor Computing-In-Memory ArchitectureAuthorsYuhao LiuXiaotao JiaJianyi YuYouguang ZhangWeisheng ZhaoCong ShiCiyan ZhengQi WeiFei QiaoCIM for LLM: A Compute-In-Memory Architecture for Efficient Large Language Model InferenceAuthorsJung-Fang KeEn-Ming HuangZhi-Wei LiuYu-Guang ChenChun-Yi LeeHRing: A Hierarchical Ring Design Method for Wavelength-Routed Optical Networks-on-ChipAuthorsZhidan ZhengMeng LianMengchu LiTsun-Ming TsengUlf SchlichtmannHydrogen: Contention-Aware Hybrid Memory Management for Heterogeneous CPU-GPU ArchitecturesAuthorsYiwei LiMingyu GaoAn Efficient and Scalable Clocking Assignment Algorithm for Multi-Threaded Multi-Phase Single Flux Quantum CircuitsAuthorsRobert AvilesXi LiLei LuZhaorui NiPeter BeerelA Multi-objective Optimization Framework of Spiking Neural Network and Neuromorphic ProcessorAuthorsYuan LiRenzhi ChenZhijie YangXun XiaoJingyue ZhaoZhenhua ZhuLei WangHuadong DaiYuhua TangWeixia XuCompression with Attention: Learning in Lower DimensionsAuthorsGaurav SinghKia BazarganAdvanced Analog Design Optimization: Comparison Between Reinforcement Learning and Heuristic AlgorithmsAuthorsMichel ChevalierAntoine VialleJules CoulonSeverin TrochutRoberto GuizzettiPascal UrardLioua LabrakRémy CellierJohn SamuelNacer AbouchiAdaptive Graph Learning for Efficient Thermal Analysis of the Chiplet System under Interface VariationsAuthorsJingbo SunZhenyu WangFrank LiuVidya A. ChhabriaYu CaoMining signal temporal logic specifications for hybrid systemsAuthorsDaniele NicolettiSamuele GerminianiGraziano PravadelliA Near-data Processing Architecture for GNN Training and Inference AccelerationAuthorsHaoyang WangShengbing ZhangZhao YangMeng ZhangRethinking DRAM Failure Prediction In Memory Reliability: An Efficient Deep Image Classification PerspectiveAuthorsZhishuai HanPijia HaoAdaP-CIM: Compute-in-Memory Based Neural Network Accelerator using Adaptive Posit and Speculative AlignmentAuthorsJingyu HeFengbin TuTim ChengChi Ying TsuiGraph Attention Network-based Sparse Format Selection for Accelerating SpMM on GPUsAuthorsDezhan TuTiandong ZhaoZhuofu TaoTianjia ZhouLei HeAn Open-Source Framework for AMS Modeling and VerificationAuthorsWilliam SalcedoSara AchourFully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference TimesAuthorsFabian LeglJonas KanticDOCTOR: Dynamic On-Chip Remediation Against Temporally-Drifting Thermal Variations Toward Self-Corrected Photonic Tensor AcceleratorsAuthorsHaotian LuSanmitra BanerjeeJiaqi GuCompressed Latent Replays for Lightweight Continual Learning on Spiking Neural NetworksAuthorsAlberto DequinoAlessio CarpegnaDavide NadaliniAlessandro SavinoLuca BeniniStefano Di CarloFrancesco ContiDistributed Inference of DL Workloads on CIM-based Heterogeneous AcceleratorsAuthorsMojtaba AlShamsKamilya SmagulovaMohammed FoudaAhmed EltawilLUTMUL: A Paradigm Shift from DSPs to LUTs for Efficient Multiplication in FPGA-Based Neural Network ComputationAuthorsYanyue XieZhengang LiDana DiaconuSuranga HandagalaMiriam LeeserXue LinHigh-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory RegionAuthorsYongping LuoPeiquan JinXiaoliang WangZhaole ChuKuankuan GuoJinhui GuoPeng XuFei LiuDistribution-Guided Fairness Calibration in LearningAuthorsYi ShengJunhuan YangZhepeng WangWeiwen JiangQian LouLei YangMACO: Model-based Adaptive Circuit Optimization by Transformer-based Bidirectional Predictions between Circuit Parameters and SpecificationsAuthorsYoungmin OhDoyun KimYoon Hyeok LeeBosun HwangDATIS: DRAM Architecture and Technology Integrated SimulationAuthorsZheng QiaoChen ZhangZhuoshan ZhouYong LiuZhigang JiRu HuangSolving Maximum Flows of Undirected Graphs by Minimizing s-t Effective Resistances of Electrical NetworksAuthorsAli AghdaeiKuilin ZhangZhuo FengAccelerating Heterogeneous Workloads Using A Reconfigurable In-Memory Computing ArchitectureAuthorsYanfeng YangYi ZouYiyang LinXianfeng SongYingbo HaoProbability Modeling for Via-Metal Open Circuit Defects Utilizing Self-Aligned Vias Process in 5nm Technology Node and BeyondAuthorsXiaojing SuJingjing LiYajuan SuYayi WeiViTSen: Enabling Vision Transformers at the Edge Through In/Near -Sensor Processing SchemesAuthorsSepehr TabrizchiFatemeh RaeiBrendan ReidyDeniz NajafiShaahin AngiziRamtin ZandArman RoohiDTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative ModelAuthorsXuanzheng WangPeng QuYouhui ZhangEvergreen: Comprehensive Carbon Modeling for Performance-Emission TradeoffsAuthorsTersiteab AdemAndrew McCrabbVidushi GoyalValeria BertaccoDefending Membership Inference Attack on Edge using Trusted Execution EnvironmentsAuthorsCheng-Yun YangGowri RamshankarSudarshan NambiarEvan MillerXun ZhangNicholas EliopoulosPurvish JajalDave TianShuo-Han ChenChiy-Ferng PerngYung-Hsiang LuA Fast IR-drop Modeling for In-RRAM Computing Considering Data AllocationAuthorsShih-Han ChangTung LinChien-Nan LiuInstruction Sequence Generation using Reinforcement Learning for Software-Based Self-Test of Processor CoresAuthorsJongseon SeoHyungmin ChoPABTG: A Pipeline Architecture for Beaver Triple Generation in Secure Multi-party ComputationAuthorsXiaolin LiWei YanHongwei LiuQinfen HaoDual-Axis ECC: Vertical and Horizontal error correctionAuthorsGiyong JungHee Ju NaSang-Hyo KimJungrae KimA Crosstalk-Aware Timing Prediction Method in RoutingAuthorsLeilei JinJiajie XuWenjie FuHao Yanlongxing shiAffinity-based Optimizations of Homomorphic Encryption Operations on Processing-in-DRAMAuthorsKevin NamHeon Hui JungHyunyoung OhYunheung PaekA Divide-and-conquer Pebbling Strategy for Oracle Synthesis in Quantum ComputingAuthorsKezhen ZhangRiling LiMingsheng YingZero-Space Cost Fault Tolerance for Transformer-based language models on ReRAMAuthorsBingbing LiGeng YuanZigeng WangShaoyi HuangHongwu PengPayman BehnamWujie WenHang LiuCaiwen DingATAFAN: Design-Friendly Aging-aware Timing Analysis Framework Based on Hybrid Graph NetworkAuthorsJinfeng YePengpeng RenChao YangYe WeiZejian CaiHaibao ChenHui FangZhigang JiQuantum Error Correction Code Decoding with Transferable TransformersAuthorsHanrui WangPengyu LiuKevin ShaoDantong LiJiaqi GuYongshan DingSong HanmROB: Multi-Level ReOrder Buffer Design with Reduced Area and PowerAuthorsSai Praneeth MadduriMingxuan HeFangping LiuSang Wook DoDon't Cache, Speculate!: Speculative Address Translation for Flash-based Storage SystemsAuthorsHyungjin KimSeongwook KimJUNHYEOK PARKGwangeun ByeonSeokin HongA Practical DRAM-based Analog PIM ArchitectureAuthorsHoon ShinRihae ParkJae W. LeeDNNPhaser: Enhancing Data Locality Using Multiphase Ring Dataflow for Spatial AcceleratorsAuthorsChia-Wei ChangJing-Jia LiouHybrid Stochastic Computing of Linear Time O(N) and Its In-Memory Computing for High PerformancesAuthorsYuhao ChenLI honggeXiaoyu GuoYinjie SongXinyu ZhuMulti-Terminal Pathfinding with Conditional Denoising Diffusion Probabilistic ModelAuthorsLeonid PopryhoInna Partin-VaisbanP-ReTi: Photonic Tensor Core for Real-Time LearningAuthorsDharanidhar DangPriyabrata DashHeterogeneous Vector Accelerator for Matrix Multiplications on FPGAAuthorsJay ShahNanditha RaoAn Efficient Framework for High-Fidelity Automotive Exterior DesignAuthorsChangdi YangZichong MengTim RuppechtCaiyue LaiEnfu NanJun LiuZhijun HiPu ZhaoYanzhi WangEfficient Memory Placement in Chiplet-Based SystemsAuthorsShant RakshitHimanshu KumarNanditha Rao
