Presentation
Planaria: Full Pattern Directed Heterogeneous Hardware Prefetcher with Efficient Bypass
DescriptionDue to the memory wall, memory system performance significantly impacts the user experience of mobile phones. The system cache (SC) locates on the memory side and is shared by all the central processing units (CPUs) and graph processing units (GPUs) within the mobile phone and is the last defense line before resorting to the time-consuming off-chip memory access. However, it is challenging to manage SC, due to the memory-side large working set and irregular accessing patterns. Although SC takes up a considerable on-chip area, the effectiveness of SC in terms of hit rate is rather low. It is observed that neither using the state-of-the-art cache replacement policies nor enlarging cache size can significantly benefit SC. The prefetchers designed for higher-level caches cannot be used by SC, because the required program counter (PC) is not available on the memory-side and/or the aggressive prefetch traffic violates the stringent power constraints of mobile phones. In this study, we propose Planaria, which includes two sub-prefetchers (SLP and TLP) and a coordinator (POC) to simultaneously achieve high accuracy and coverage of prefetching. The two sub-prefetchers exploit the intra- and inter-page regularities via self and transfer learning, respectively. The coordinator POC explicitly decouples the learning and issuing phases of the sub-prefetchers. The sub-prefetchers are directed by the full pattern, but are enabled in an irreversible order. The working fashion of "parallel training and serial issuing'' effectively increases useful prefetches and reduces useless prefetches. Experimental results show that, Planaria has improved the overall system performance in terms of instructions per cycle (IPC) by 28.9%, 21.9% and 15.3% on average over no prefetcher and BOP and SPP, respectively. Moreover, Planaria only incurs 0.5% power consumption overhead, while BOP and SPP increase the power consumption by 13.5% and 9.7%, respectively.
Event Type
Research Manuscript
TimeTuesday, June 255:00pm - 5:15pm PDT
Location3012, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures