Session

DescriptionThis session presents significant advancements in the design of application-specific accelerators and cache memory challenges. This session presents accelerators for sparse matrix multiplication through a novel co-design approach, a reformulated Winograd convolution, a Bayes Neural Networks as well as for mitigation of manufacturing security risks owing to the design of a novel ASIC. Additionally, novel results of a ultra-fast, knowledge-based HLS design optimization method and a coarse-grained reconfigurable architecture (CGRA) acceleration framework for end-to-end homomorphic applications are presented. Regarding the cache memory challenges, advancements on the development of a shared memory expansion method for GPU and two novel sub-prefetchers are provided.