Presentation
zeroTT: A Two-Step State Transition Avoidance Scheme for MLC STT-RAM
DescriptionCompared with conventional SRAM, Spin-Transfer Torque Random Access Memory(STT-RAM) is expected to play a crucial role in future memory technologies with the increasing demands for higher storage density and lower power consumption for modern embedded systems. Moreover, Multi-Level Cell (MLC) STT-RAM outperforms Single-Level Cell (SLC) STT-RAM since it can store multiple bits per cell. However, MLC STT-RAM suffers from the occurrence of two-step state transitions (TTs) due to additional flipping of soft domains. Existing approaches mitigate this problem by reducing TTs with data coding. However, none of them can eliminate all the TTs. In this work, we propose a two-step transition avoidance scheme, referred to as zeroTT, for MLC STT-RAM. We show why the existing (2,3)-based coding methods cannot avoid TTs. Then, we refine the problem of expansion coding and present how to find zeroTT coding methods. Lastly, we propose an optimal (3,4)-based coding method considering the issues of space overhead and coding complexity. The experimental results demonstrate that zeroTT can completely avoid TTs, leading to a more efficient MLC STT-RAM in terms of latency, energy consumption, and lifetime.
Event Type
Research Manuscript
TimeThursday, June 272:00pm - 2:15pm PDT
Location3008, 3rd Floor
Embedded Systems
Embedded Memory and Storage Systems