Presentation
AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs
DescriptionResearchers and industries are increasingly drawn to quantum computing solutions, attracted by their potential computational advantages over classical systems. However, validating new quantum algorithms faces challenges due to limited qubit availability and noise in current quantum devices. Software simulators offer a solution but are time-consuming. Hardware emulators are emerging as an attractive alternative.
This article introduces AMARETTO (quAntuM ARchitecture EmulaTion TechnOlogy), an architecture designed for quantum computing emulation on low-tier Field Programmable Gate Arrays (FPGAs) supporting Clifford+T and rotational gate sets. AMARETTO accelerates and simplifies the functional verification of quantum algorithms using a Reduced-Instruction-Set-Computer (RISC)-like structure and efficient handling of sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. Our results, validated against the Qiskit state vector simulator, demonstrate successful emulation of 16 qubits on a Xilinx Kria KV260 System on Module (SoM). This approach rivals other works in the literature, offering similar emulated qubit capacity on a smaller, more accessible FPGA.
This article introduces AMARETTO (quAntuM ARchitecture EmulaTion TechnOlogy), an architecture designed for quantum computing emulation on low-tier Field Programmable Gate Arrays (FPGAs) supporting Clifford+T and rotational gate sets. AMARETTO accelerates and simplifies the functional verification of quantum algorithms using a Reduced-Instruction-Set-Computer (RISC)-like structure and efficient handling of sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. Our results, validated against the Qiskit state vector simulator, demonstrate successful emulation of 16 qubits on a Xilinx Kria KV260 System on Module (SoM). This approach rivals other works in the literature, offering similar emulated qubit capacity on a smaller, more accessible FPGA.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
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