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Work-in-Progress Poster: Tuesday Work-in-Progress Posters

Event TypeWork-in-Progress Poster

TimeTuesday, June 256:00pm - 7:00pm PDT

LocationLevel 2 Lobby

Topics

Presentations

HPA: A novel IS-WS hybrid data flow for PIM architectures Authors Yun Zhao Sheng Ma Heng Liu Li Huang Li Wu Jian Zhang Chun Zhang Tie Li
Understanding the Upper Bounds of Energy Efficiency in a Computing-in-Memory Processor and How to Approach the Limit Authors Zhaori Cong Jinshan Yue Shengzhe Yan Zhuoyu Dai Zeyu Guo Zhihang Qian Yifan He sun wenyu Chunmeng Dou Feng Zhang Yongpan Liu
Additive Partial Sum Quantization Authors Pingcheng Dong Yonghao Tan Dong Zhang Yongkun Wu Xijie Huang Shi-Yang Liu Yu Liu Xuejiao Liu Peng Luo Luhong Liang Fengwei An Kwang-Ting Cheng
From RTL to Prompt: AN LLM-assisted Verification Methodology for General Processor Authors Yifei Deng Chao Xiao Zhijie Yang Renzhi Chen Yuanfeng Luo Jingyue Zhao Huadong Dai Lei Wang Yuhua Tang Weixia Xu
An Effective Timing Driven Placement with Accurate Differentiable Timing Approximation Integration Authors Xu He Renjun Zhao Chenjing Yang Yushan Wang Yao Wang Peiyu Liao Yibo Lin Bei Yu
SPHINCSLET - A Lightweight Implementation of SPHINCS+ Authors Sanjay Deshpande Yongseok Lee Cansu Karakuzu Jakub Szefer Yunheung Paek
Learned Index Acceleration with FPGAs: A SMART Approach Author Geetesh More
TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-Tree Authors Xing Wang Tianhui Jiao Yuchen Ma Zhican Zhang Zhichao Liu Xi Chen Xin Si
PixelPrune: Sparse Object Detection for AIoT Systems via In-Sensor Segmentation and Adaptive Data Transfer Authors MohammadReza Mohammadi Mehrdad Morsali Brendan Reidy Sepehr Tabrizchi Mohsen Imani Arman Roohi Shaahin Angizi Ramtin Zand
Scaler-FFT: A Scalable FPGA-based FFT Accelerator via General Matrix Multiplication Authors Song Zhang Zhiyuan Ma Zexu Zhang Yueyin Bai Kun Wang
Addressing the Diversity in AI Computing: An On-chip Programmable Accelerator Authors Gopikrishnan Raveendran Nair Fengyang Jiang Jeff Zhang Jae-sun Seo Yu Cao
Interactive Visual Performance Space Exploration of Analog ICs with Neural Network Surrogate Models Authors Yannick Uhlmann Till Moldenhauer Jürgen Scheible
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring Authors Dimitrios Tsaras Lei Chen Xing Li Weihua Sheng Zhiyao Xie Mingxuan Yuan
A Quantum Solver for the Boolean Matching Problem Authors Marco Venere Alessandro Barenghi Gerardo Pelosi
TinySeg: Memory-efficient Image Segmentation for Small Embedded Systems Authors Byungchul Chae Jiae Kim Seonyeong Heo
Pre-Silicon Power Side-channel Leakage Assessment of CRYSTALS-Kyber Authors Nashmin Alam Tao Zhang Farimah Farahmandi
Tripartite Server Mutual Attestation: TEE-based BFT for Boosting Server Reliability in Federated Learning Authors Yusen Wu Phuong Nguyen Yelena Yesha
Pushing Computing-in-memory towards Computational Storage to Accelerate In-Orbit Remote Sensing Satellite Image Processing Authors Hongyang Hu Shengwen Liang Kai Xi Zizhen Liu Jinshan Yue Dashan Shang Xiaoxin Xu Jing Liu Chunmeng Dou Ming Liu
CDA: Collaborative Computing Using Centralized-Distributed Architecture for Smart Sensing Authors Erxiang Ren Cheng Qu Li Luo Yonghua Li Zheyu Liu Xinghua Yang Qi Wei Fei Qiao
An Application of Information Flow Tracking to Hardware Trojan Detection Authors Ryoichi Isawa Nobuyuki Kanaya Daisuke Inoue
Integrated MAC-based Systolic Arrays: Design and Performance Evaluation Authors Dantu Nandini Devi Gandi Ajay Kumar Bindu G Gowda Madhav Rao
Methodology to define, design and support ultra-low voltage Digital Design Authors Arnab Khawas Varun Ithal Badarish Subbnnavar
AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs Authors Christian Conti Deborah Volpe Mariagrazia Graziano Maurizio Zamboni Giovanna Turvani
Deputy NoC: A Case of Low Cost Network-on-Chip for Neural Network Accelerations on GPUs Authors Khoa Ho Siamak Biglari Justin Garrigus Hui Zhao
RADAR: A Skew-resistant and Hotness-aware Ordered Index Design for Processing-in-memory Systems Authors Yifan Hua Shengan Zheng Weihan Kong Cong Zhou Kaixin Huang Ruoyan Ma Yifeng Hui Linpeng Huang
Quantifying the Energy Efficiency Benefits of Monolithic 3D Refreshless Embedded-DRAM Authors David Kong Shvetank Prakash Jedrzej Kufel Georgios Kyriazidis Yasmine Omri David Verity Emre Ozer Vijay Janapa Reddi Gage Hills
QuBound: An Efficient Workflow Enabling Prediction of Performance Bounds under Unpredictable Quantum Noise Authors jinyang li Samudra Dasgupta Travis Humble Weiwen Jiang
NeuroSteiner: A Graph Transformer for Wirelength Estimation Authors Sahil Manchanda Dana Kianfar Markus Peschl Romain Lepert Michael Defferrard
SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation Authors Shams Tarek Dipayan Saha Sujan Kumar Saha Mark Tehranipoor Farimah Farahmandi
A High-Throughput, Energy-Efficient, and Constant-Time In-SRAM AES Engine with Massively-Parallel Bit-Serial Execution Authors Andrew Dervay Wenfeng Zhao
The chipSECS Hardware Trojan Benchmark Suite and Verification Methodology Author Christian Krieg
Are Adversarial Examples Suitable To Be Test Suites for Testing Deep Neural Networks Author Wei Kong
An Analytical Fidelity Model for Readout Circuitry with Multiple Co-Existing Non-Idealities for Superconducting Quantum Computing Authors Yao Tong Quan Chen
The Power of Graph Signal Processing for Chip Placement Authors Yiting Liu Hai Zhou Jia Wang Fan Yang Xuan Zeng Li Shang
GPU-Accelerated BFS for Dynamic Networks Authors Filippo Ziche Rosalba Giugno Federico Busato Nicola Bombieri
AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multibit Compute and Interconnect Authors Zihao Xuan Song Chen Kang Yi
AutoFlow: Inferring Message Flows From System Communication Traces Authors Bardia Nadimi Hao Zheng
Adaptive Neurosurgeon: DNN Computing Latency Minimization for Mobile Edge Intelligence Authors Gang Wu Qianru Wang Biao Hu
ESFA: An Efficient Scalable FFT Accelerator Design Framework on Versal AI Engine Authors Hao Yang Linfeng Du Wei Zhang
Exploring Distributed Circuit Design Using Single-Step Reinforcement Learning Authors Jiayu Li Masood Mortazavi Ning Yan
Enabling Fast 2-bit LLM on GPUs: Memory Alignment, Sparse Outlier, and Asynchronous Dequantization Authors Jinhao Li Shiyao Li Jiaming Xu Shan Huang Jun Liu Yaoxiu Lian Yu Wang Guohao Dai
FastSample: Accelerating Distributed Graph Neural Network Training for Billion-Scale Graphs Authors Hesham Mostafa Adam Grabowski Md Asadullah Turja Juan Cervino Alejandro Ribeiro Nageen Himayat
On Optimization of Robustness of Inter- and Intra-chiplet Interconnection Topology for Multi-chiplet Systems Authors Miao Xu Xiaohang Wang Amit Kumar Singh Yingtao Jiang Mei Yang
Methodology of configurable memory conflict-free Number Theoretic Transform accelerator for FPGA platform Authors Xiangchen Meng Yangdi Lyu
Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories Authors Rakshith Saligram Amol Gaidhane Suman Datta Yu Cao Arijit Raychowdhury
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems Authors Ankur Limaye Nicolas Bohm Agostini Claudio Barone Vito Giovanni Castellana Michele Fiorito Fabrizio Ferrandi Andres Marquez Antonino Tumeo
A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing Authors Limin Jiang Yi Shi Haiqin Hu Qingyu Deng Siyi Xu Yintao Liu Feng Yuan Si Wang Yihao Shen Fangfang Ye Shan Cao Zhiyuan Jiang
Scalable Multi-task Deep Inference on Resource Constrained Energy Harvesting System Authors Sahidul Islam Bin Lei Shanglin Zhou Chen Pan Caiwen Ding Mimi Xie
Analytical Modeling and Electro-Thermal Benchmarking of 2.5D/3D Heterogeneous Integration for AI Computing Authors Zhenyu Wang Jingbo Sun A. Alper Goksoy Sumit Mandal Jae-sun Seo Vidya A. Chhabria Jeff Zhang Chaitali Chakrabarti Umit Ogras Yu Cao
From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches Authors Marcelo Orenes-Vera Margaret Martonosi David Wentzlaff
Representation-Independent Resubstitution for Area-Oriented Logic Optimization Authors Andrea Costamagna Alessandro Tempia Calvino Alan Mishchenko Satrajit Chatterjee Siang-Yun Lee Giovanni De Micheli
Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM) Authors Dhandeep Challagundla Ignatius Bezzam Riadul Islam
ODILO: On-Device Incremental Learning Via Lightweight Operations Authors Qing Wang Di Liu Shengfa Miao Mingxiong Zhao
Optimal Toffoli-Depth Quantum Adder Authors Siyi Wang Ankit Mondal Anupam Chattopadhyay
Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators Authors Stijn Ringeling Marco Fattori Shagun Bajoria Robert Rutten Lucien Breems Eugenio Cantatore
Principles for Enabling TEEs on Domain-Specific Accelerators Authors Aritra Dhar Supraja Sridhara Shweta Shinde Srdjan Capkun Renzo Andri
Enhancing Performance of Deep Neural Networks with a Reduced Retention-Time MRAM-Based Memory Architecture Authors Munhyung Lee Taehan Lee Junwon Yeo Hyukjun Lee
TDM: Time and Distance based Metric for Quantifying Information Leakage Vulnerabilities in SoCs Authors Avinash Ayalasomayajula Hasan Al-Shaikh Henian Li Sujan Saha Farimah Farahmandi
Where and How to Charge: Effective Charging with Mobile Agent in Wireless Powered CPS Authors Chenchen Fu Zining Zhou Sujunjie Sun Weiwei Wu Song Han
SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration Authors Xu He Yushan Wang Renjun Zhao Yao Wang Chang Liu Yang Guo
Operational Safety in Human-in-the-loop Human-in-the-plant Autonomous Systems Authors Ayan Banerjee Aranyak Maity Imane Lamrani Sandeep Gupta
Hyft: A Reconfigurable Softmax Accelerator with Hybrid Numeric Format for both Training and Inference Authors Tianhua Xia Sai Qian Zhang
Optimizing Homomorphic Convolution for Private CNN Inference Authors Hyeri Roh Woo-Seok Choi
Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation Authors Dongho Kim Seokhun Kim Junseo Lee Hongwon Kim Sangheon Lee Jihwan Park Hanwool Jeong
A Hardware-Aware Framework for Practical Quantum Circuit Knitting Authors Xiangyu Ren Mengyu Zhang Shengyu Zhang Yicong Zheng Antonio Barbalace
FEI: Fusion Processing of Sensing Energy and Information for Self-sustainable Infrared Smart Vision System Authors Xin Hong Haijin Su Maimaiti Nazhamaiti Ce Zhang Junkai Huang Yuzhao Yang Li Luo Qi Wei Zheyu Liu Fei Qiao
SFQ counter-based precomputation for large-scale cryogenic VQE machines Authors Yosuke Ueno Satoshi Imamura Yuna Tomida Teruo Tanimoto Masamitsu Tanaka Yutaka Tabuchi Koji Inoue Hiroshi Nakamura
VisionHD: Revisiting Hyperdimensional Computing for Improved Image Classification Authors Fatemeh Asgarinejad Justin Morris Tajana Rosing Baris Aksanli
Escaping local optima in global placement Authors Ke Xue Xi Lin Yunqi Shi Shixiong Kai Siyuan Xu Chao Qian
PIANIST: Efficient Quantum Circuit Simulation using Commercial Processing-in-Memory System Authors Dongin Lee Enhyeok Jang Seungwoo Choi Junwoong An Cheolhwan Kim Won Woo Ro
Labidus: Productive Accelerator Development via Configurable Soft Processors Authors Gongjin Sun Seongyoung Kang Jane He Sang-Woo Jun
Approx-T: Design Methodology for Approximate Multiplication Units via Taylor-expansion Authors Shang-shang YAO Qing-jie LANG Li Shen Kai LU
NeuCore: A Novel Neuromorphic Processor Architecture with On-chip Event-driven Learning Authors Yi Wei zhijie Yang Xun Xiao xiangyu Wang junbo Tie jingyue Zhao Lei Wang huadong Dai weixia Xu yuhua Tang zhenhua Zhu
CellRejuvo: Rescuing the Aging of 3D NAND Flash Cells with Dense-Sparse Cell Reprogramming Authors Han-Yu Liao Yi-Shen Chen Jen-Wei Hsieh Yuan-Hao Chang Hung-Pin Chen
Hardware-Accelerated Optimization of DSP-Based Equalizer in High-Speed ADC-Based Receivers Authors Yoona Lee Hanseok Kim Jin-Seok Heo Woo-Seok Choi
A Parallel-trial Double-update Annealing Algorithm for Enabling Highly-effective State Transition on Annealing Processors Authors Akira Hyodo Satoru Jimbo Daiki Okonogi Genta Inoue Thiem Chu Masato Motomura Kazushi Kawamura
Efficient Synaptic Delay Acceleration in Digital Event-Driven Neuromorphic Processors Authors Roy Meijer Paul Detterer Amirreza Yousefzadeh Alberto Patiño-Saucedo Guangzhi Tang Kanishkan Vadivel Yingfu Xu Mario Konijnenburg Manil Dev Gomony Federico Corradi Manolis Sifalakis
B-Ring:An Efficient Interleaved Bidirectional Ring All-reduce Algorithm for Gradient Synchronization Authors Ruixing Zong Jiapeng Zhang Guoqing Xiao Zhuo Tang Kenli Li
A novel method to analysis the wafer defect patterns using an image matching algorithm based on deep neural networks Authors Youngwook Kwon Sumin Oh HyunJin Kim
Multi-modal Signal applied Neuromorphic proven SNN Model for Stress Detection Authors Ajay BS Madhav Rao
SASDynabLE: A Compact Transformer Inference Architecture with Saturation-Approximate Softmax Enabling Dynamic-Mapping Based Layer-Fusion Execution Authors Liu He Zongle Huang Yujin Wang Shupei Fan Tang Chen Huazhong Yang Yongpan Liu Hongyang Jia
Reset Domain Crossing Design Verification Closure using Advanced Data Analytics Techniques Authors REETIKA REETIKA Sulabh Khare
MatHE: A Near-Mat Processing In-Memory Accelerator for Fully Homomorphic Encryption Authors Minxuan Zhou Yujin Nam Pranav Gangwar Weihong Xu Arpan Dutta Chris Wilkerson Rosario Cammarota Saransh Gupta Tajana Rosing
Athena: Add More Intelligence to RMT-based Network Data Plane with Low-bit Quantization Authors Yunkun Liao Hanyue Lin Jingya Wu Wenyan Lu Xiaowei Li Guihai Yan
nvmXR: Design Space Exploration of Non-Volatile Memory Architectures for Edge-XR Systems Authors Zihan Zhang Marco Donato
Libra: Collaborating with Basis-Inverted Circuits to Mitigate State-Dependent Errors on NISQ Programs Authors Enhyeok Jang Youngmin Kim Won Woo Ro
LEAP: Layout aware Estimation of Analog design Parasitics Authors Prasanth Mangalagiri Siddhartha Joshi
GNN-Opt: Enhancing Automated Circuit Design Optimization with Graph Neural Networks Authors Kazuya Yamamoto Nobukazu Takai
Navigating the Challenges of Statistical Fault Injection in SRAM-FPGA Authors Trishna Rajkumar Johnny Oberg
A General Purpose IMC Architecture with ADC-Awared Neural Networks Authors Min-Gwon Song Shin-Uk Kang Min-Seong Choo
Multi-modal Signal applied Dynamic neuron based Spike processor for Stress Detection Authors Ajay BS Phani Pavan Madhav Rao
Balancing and Minimizing Energy Consumption of Federated Learning in Heterogeneous Mobile Edge IoT Authors Zehao Ju Tongquan Wei

DAC 2024