Presentation
Bayesian learning-driven Memory Design Exploration with Automated Circuit Variant Generation
DescriptionThis paper proposes Bayesian learning driven automated embedded memory design methodology that aims to minimize power consumption and/or maximize performance while meeting predefined constraints. To achieve this objective effectively, we present an automatic tool that leverages a reference initial circuit design to generate a diverse set of schematic and layout options for logic-equivalent circuit variants. Subsequently, leveraging the range of circuit options generated, Bayesian optimization is employed not only to identify optimal circuit parameters but also to select the most appropriate circuit topology to attain the desired design objectives. TSMC 28nm process simulation results demonstrate the proposed methodology reducing dynamic power by 21.59%-39.02% and access time by 29.45%-38.21% compared to the compiler-generated design, with a runtime of 10-40 hours.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security