Presentation
Unleashing the Power of T1-cells in SFQ Arithmetic Circuits
DescriptionSuperconductive rapid single-flux quantum (RSFQ) ICs dissipate 10-100 smaller power w.r.t. CMOS while operating at tens of GHz. The issue of path balancing in RSFQ systems however incurs significant area overhead, particularly severe due to limited layout density of RSFQ fabrication.
The SFQ T1-cell realize the full adder function with 60% less area compared to conventional implementation. This cell however imposes complex input timing constraints. With multiphase clocking, the T1-cell input timing can be efficiently satisfied. Here, we propose SFQ technology mapping methodology supporting T1-cells. The area of the arithmetic SFQ networks is reduced by up to 25%.
The SFQ T1-cell realize the full adder function with 60% less area compared to conventional implementation. This cell however imposes complex input timing constraints. With multiphase clocking, the T1-cell input timing can be efficiently satisfied. Here, we propose SFQ technology mapping methodology supporting T1-cells. The area of the arithmetic SFQ networks is reduced by up to 25%.
Event Type
Research Manuscript
TimeTuesday, June 254:45pm - 5:00pm PDT
Location3002, 3rd Floor
Design
Emerging Models of Computation