Presentation
STAGGER: Enabling All-in-One Subarray Sensing for Efficient Module-level Processing in Open-Bitline ReRAM
DescriptionEmerging resistive RAM (ReRAM) devices can in-situ execute vector-matrix-multiplication (VMM) for scientific computing. However, the peripheral separated S&Hs and ADCs for row buffering and sensing in conventional designs are the system bottleneck. We propose an ADC-less all-in-one subarray-VMM-sensing design that enables the precharge once, readout multiple-bits functionality. We propose a cascaded-feedback bitline sensing architecture and a buffering-and-sensing-collocated sense amplifier design with bitline and storage node fully decoupled for enabling conflict-free column accesses. We further propose cross-level interleaving for successive VMM accesses. Experimental results show that our design achieves 297% performance improvement and 85.8% energy reduction, compared with an aggressive baseline.
Event Type
Research Manuscript
TimeTuesday, June 254:00pm - 4:15pm PDT
Location3002, 3rd Floor
Design
Emerging Models of Computation