Presentation
AdderNet 2.0: Optimal FPGA Acceleration of AdderNet with Activation-Oriented Quantization and Fused Bias Removal based Memory Optimization
DescriptionEmerging proposals, such as AdderNet, exploit efficient arithmetic alternatives to the Multiply-ACcumulate (MAC) operations in convolutional neural networks (CNNs). AdderNet adopts an ℓ1-norm based feature extraction kernel, which shows nearly identical model accuracy as compared to the CNN counterparts and can achieve considerable hardware savings due to simpler Sum-of-Absolute-Difference (SAD) operations. Nevertheless, existing AdderNet-based accelerator designs still face critical implementation challenges, such as inefficient model quantization, excessive feature memory overheads, and sub-optimal resource utilization. This paper presents AdderNet 2.0, an optimal AdderNet based accelerator architecture with a novel Activation-Oriented Quantization (AOQ) strategy, a Fused Bias Removal (FBR) scheme for on-chip feature memory bitwidth reduction, and an improved PE design to improve resource utilization. The proposed AdderNet 2.0 accelerator designs were implemented on Xilinx Kria KV-260 FPGA. Experimental results show that INT6 accelerator design achieves up to 3.78× DSP density improvement, and 24% LUT, 40% FF, and 2.1× BRAM savings compared to the baseline CNN design.
Event Type
Research Manuscript
TimeTuesday, June 254:45pm - 5:00pm PDT
Location3004, 3rd Floor
AI
Design
AI/ML, Digital, and Analog Circuits