Presentation
CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis
DescriptionIn advanced process technology nodes, analog circuit performance is intrinsically linked to layout parasitics, and layout dependent effects (LDE). In contrast to digital designs, layout generation for analog mixed signal circuits remains predominantly a slow manual task, impeding rapid design convergence. To address this bottleneck, we introduce CDLS - a Constraint Driven Generative AI Framework for Analog Layout Synthesis. CDLS is fundamentally a constraint driven framework that enables analog circuit designers to auto-generate simulation-ready layout. Unlike traditional algorithmic approaches, CDLS uses generative AI and machine learning techniques to generate key design constraints that drive the quality of autogenerated placement and routing. Using CDLS on average we reduce layout iteration time by 2-3X on industrial designs. By reducing the turn-around-time on layout iterations we estimate a 30% reduction to overall design convergence cycle. We also demonstrate the quality of results achieved through CDLS is on par with manual drawn layout, on state-of-the-art analog designs developed on an Intel sub-10nm process technology node.
Event Type
Research Manuscript
TimeTuesday, June 255:00pm - 5:15pm PDT
Location3004, 3rd Floor
AI
Design
AI/ML, Digital, and Analog Circuits