Presentation
Addressing the Diversity in AI Computing: An On-chip Programmable Accelerator
DescriptionAI algorithms are increasingly diverse, from dense to sparse, and from regular to irregular. To efficiently manage such diversity in hardware, we propose a programmable heterogeneous accelerator that dynamically balances the computation requirements across different design levels. It comprises two types of processing elements (PEs) customized for dense (e.g., DNNs) and sparse (e.g., graphs) workloads, respectively. These PEs are integrated into a programmable architecture, enabling support for various memory access and computation patterns. Based on 16nm design data, the new accelerator achieves a 11x improvement in latency compared to state-of-the-art homogeneous accelerators.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security