Presentation
Probability Modeling for Via-Metal Open Circuit Defects Utilizing Self-Aligned Vias Process in 5nm Technology Node and Beyond
DescriptionThe budget is constrained by the process variations at of 5nm technology node and beyond. Greater attention will be required self-aligned via process. A probability model of via-metal open circuit defects is proposed to quantify the main uncertainty factors accurately. CD variabilities of lithography processes and displacements induced by overlay along critical direction are considered. Our model outperforms the Monte Carlo method by achieving an average deviation below 0.1%, while being at least two orders of magnitude faster in calculation speed. Our probability model can lead to a more robust design, enhancing the overall pattern quality with short turn-around-time.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
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Design
EDA
Embedded Systems
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Security