Presentation
CirSTAG: Circuit Stability Analysis via Graph Neural Networks
DescriptionCircuit stability (sensitivity) analysis aims at estimating the overall performance impact due to the perturbations of underlying design parameters (e.g. gate sizes, capacitance variations, etc), which remains a challenging task since many time-consuming circuit simulations are typically required. On the other hand, graph neural networks (GNNs) have proven to be effective in solving many chip design automation problems, including circuit timing prediction, parasitics prediction, gate sizing, and device placement. This paper presents a novel approach (CirSTAG) that exploits GNNs to analyze the stability (robustness) of modern integrated circuits (ICs). CirSTAG is based on a spectral framework for analyzing the stability of GNNs leveraging input/output graph-based manifolds: when two nearby nodes on the input manifold are mapped (through a GNN model) to two distant nodes (data samples) on the output manifold, it implies a large distance mapping distortion (DMD) and thus poor GNN stability. CirSTAG computes a stability score equivalent to the local Lipschitz constant for each node/edge considering both graph structural and node feature perturbations, which immediately allows for identifying the most critical (sensitive) circuit elements that would significantly alter the circuit performance. Our empirical evaluations on a variety of timing prediction tasks with realistic circuit designs show that CirSTAG can truthfully estimate each circuit element's stability under various parameter perturbations, offering a scalable approach for assessing the stability of large IC designs.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security