Presentation
The Power of Graph Signal Processing for Chip Placement
DescriptionPlacement is a critical yet computationally complex task. Modern analytical placers suffer a long placement iteration time. Recent efforts to expedite this process incorporate deep learning.
However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics.
This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. It can be seamlessly integrated with modern analytical placers, yielding high-quality placement solutions with significantly reduced iteration time. Experimental results show that state-of-the-art placers equipped with GiFt can achieve over 50% reduction in total runtime.
However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics.
This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. It can be seamlessly integrated with modern analytical placers, yielding high-quality placement solutions with significantly reduced iteration time. Experimental results show that state-of-the-art placers equipped with GiFt can achieve over 50% reduction in total runtime.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security