Presentation
Navigating the Challenges of Statistical Fault Injection in SRAM-FPGA
DescriptionIn the traditional statistical injection, uncertainty regarding failure rates leads to adopting conservative assumptions that maximise sample size. Consequently, fault injection experiments become excessively time-consuming for applications with minimal error margins. To mitigate the limitations of existing approaches, we investigate the potential of Bayesian sampling in minimising the sample size. Preliminary results indicate up to 5X reduction with an error rate consistently below 1%.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security