Presentation
Efficient Memory Placement in Chiplet-Based Systems
DescriptionMemory bandwidth, types of compute elements and the NoC play key roles in designing a chiplet-based accelerator. In this work, we investigate the strategic placement of memory chiplets to ensure efficient data access, optimized throughput, and maximal utilization of hardware resources. We model an architecture with 64 compute chiplets, 16 memory chiplets, and 16 I/O chiplets. We evaluate six architectures with different memory chiplet placements and propose a clustered-memory configuration which results in an 8% reduction in average latency, 22% reduction in packet latency, and 20% gain in average throughput compared to a baseline architecture.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security