Presentation
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization
DescriptionComputing-in-memory has demonstrated great energy-efficiency by integrating computing units into memory. However, previous research on CIM has rarely utilized sparsity in activation and weight concurrently. Thus, we implemented an accelerator called Dyn-Bitpool which innovates on two fronts: 1) a balanced working scheme called "pool first and cross lane sharing" to maximize the performance benefiting from bit-level sparsity in activation; 2) dynamic topology of CIM arrays to effectively handle low hardware utilization issue stemming from value-level sparsity in weight. All the contributions collaborate to speed up Dyn-Bitpool by 1.89x and 2.64x on average compared with two state-of-the-art accelerators featuring CIM.
Event Type
Research Manuscript
TimeTuesday, June 255:15pm - 5:30pm PDT
Location3003, 3rd Floor
Design
In-memory and Near-memory Computing Circuits