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Research Manuscript: STCO for Embedded Compute in Memory Devices and Circuits

Session Chairs

DescriptionCompute in Memory (CIM) is a promising approach to mitigate the data movement energy and latency costs in modern data-intensive workload applications. This session brings in recent developments in emerging embedded memory devices, circuits, design methodologies, and their impact on the system-level power performance metrics for various workloads.

Event TypeResearch Manuscript

TimeTuesday, June 253:30pm - 5:30pm PDT

Location3003, 3rd Floor

Topics

Keywords

Presentations

3:30pm - 3:45pm PDT	Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency Authors Weiliang Huang Jinyu Bai Wang Kang Zhaohao Wang kaihua cao hongxi liu He Zhang Weisheng Zhao
3:45pm - 4:00pm PDT	EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration Authors Haoyi Zhang Jiahao Song Xiaohan Gao Xiyuan Tang Yibo Lin Runsheng Wang Ru Huang
4:00pm - 4:15pm PDT	Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference Authors Qilin Zheng Ziru Li Jonathan Ku Yitu Wang Brady Taylor Deliang Fan Yiran Chen
4:15pm - 4:30pm PDT	Synthesis of Compact Flow-based Computing Circuits from Boolean Expressions Authors Sven Thijssen Muhammad Rashedul Haq Rashed Sumit Jha Rickard Ewetz
4:30pm - 4:45pm PDT	CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm Authors Zhiheng Yue Shaojun Wei Yang Hu Shouyi Yin
4:45pm - 5:00pm PDT	ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM Authors Jonathan Ku Junyao Zhang Haoxuan Shan Saichand Samudrala Jiawen Wu Qilin Zheng Ziru Li Jeyavijayan Rajendran Yiran Chen
5:00pm - 5:15pm PDT	Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator Authors Weikai Xu Jin Luo Qianqian Huang Ru Huang
5:15pm - 5:30pm PDT	Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization Authors Xujiang Xiang Zhiheng Yue Yuxuan Li Liuxin Lv Shaojun Wei Yang Hu Shouyi Yin

DAC 2024