Presentation
Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference Times
DescriptionWe propose an efficient and generic Field-Programmable Gate Array (FPGA) implementation of Reservoir Computing using Linear Cellular Automata models for the application of time series processing. Our implementation results from a fully automated model definition to FPGA bitstream design automation process. Hence, it significantly reduces the design time and complexity. It can be clocked with at least 475 MHz on a Xilinx Zynq Ultrascale+ FPGA
while performing one prediction in every clock cycle. Since our implementation only uses lookup tables and registers, it is platform independent. It thus can not only be run on high-performance but also on low-cost FPGAs without special hardware components. Being up to six orders of magnitudes faster than other Reservoir Computing model implementations, our implementation enables intelligent real-time sensor signal processing for applications requiring MHz sampling rates, like structure-borne noise monitoring or high-frequency oscillation analysis.
while performing one prediction in every clock cycle. Since our implementation only uses lookup tables and registers, it is platform independent. It thus can not only be run on high-performance but also on low-cost FPGAs without special hardware components. Being up to six orders of magnitudes faster than other Reservoir Computing model implementations, our implementation enables intelligent real-time sensor signal processing for applications requiring MHz sampling rates, like structure-borne noise monitoring or high-frequency oscillation analysis.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
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