Presentation
Enhancing Performance of Deep Neural Networks with a Reduced Retention-Time MRAM-Based Memory Architecture
DescriptionDeep Neural Network (DNN) applications demanding high memory bandwidth present a significant challenge. DNNs contain weight and activation data. Weight data are only read during inference, whereas activation data are modified to store intermediate results. We propose a reduced retention-time MRAM-based main memory, where MRAM is divided into two partitions with different retention times. In this scheme, DNN weights are mapped to the long retention-time partition, while activation data can be mapped to the short retention-time partition. Two circular buffer mapping schemes demonstrate an average improvement of up to 14.4 % over DRAM in bandwidth.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security