Presentation
A Practical DRAM-based Analog PIM Architecture
DescriptionWe propose PRADA, a practical DRAM-based analog PIM architecture. Unlike existing proposals, PRADA does not introduce any change to the cell area to implement NOT operation. PRADA proposes two states in the bitline sense amplifier to implement NOT operation without additional circuitry. We also introduce sequential row activation to enhance the throughput performance and not to modify the row decoder. Compared to state-of-the-art analog PIM architectures, PRADA demonstrates 2.67-4.79x higher throughput for 8-bit integer multiply. For vector-ADD, PRADA achieves 3.09-3.13x speedups over the baseline, which compares favorably to the other architectures with 1.04-2.07x speedups, while maintaining superior compatibility and reliability.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
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