Presentation
Dual-Axis ECC: Vertical and Horizontal error correction
DescriptionDRAM has evolved across generations by increasing its transfer rates in response to computer system's growing demand for bandwidth. However, higher transfer rates have increased the likelihood of errors known as link errors, occuring during the data transmission process. Because the existing Rank-Level ECC(RL-ECC) employed by system companies is not sufficient to cope with new threats, CRC (Cyclic Redundancy Check) has been adopted in recent memory architecture to address this issue. But CRC comes with the drawback of requiring additional transfers, which lead to performance degradation. Moreover, since CRC can only detect, it triggers re-transmission in the system for correction Which may be additional overhead for systems. This paper proposes a novel RL-ECC, Dual-Axis ECC, that can also provide CRC's detection capability, ensuring there is no performance degradation due to additional transfers and mitigating re-transmission while still fulfilling RL-ECC's original purpose by exploiting unused syndromes of QPC. Our evaluation shows that compared to QPC with CRC, Dual-Axis ECC without CRC can provide same reliability level. Moreover, It can speed up applications by average 2.52\%, up to 4.88\%.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security