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Organization

Intel
Contributors
Justin Aguilar
Gilboa Alin
Subba Ramkumar Reddy Annapalli
Ponsankar Arumugam
James Bae
Susanne Balle
Suvadeep Banerjee
Gaurav Bhatia
Rosario Cammarota
Abhishek Chakraborty
Bryant Chang
Phoebe Chang
Nikhil Chawla
Igor Chervatyuk
Kurt Chu
Veera Dasari
Daniel Dinu
Raj Dua
Keshavkumar Durgakeri
Navid Farazmand
Gavriel Gavrielov
Jagadeesh Gnanasekaran
Adam Grabowski
Aarti Gupta
Sivaramakrishnan Harihara Subramanian
Nageen Himayat
Dean Huang
Lalitha Immaneni
Anshul Jain
Ritesh Jain
Srinivas Jammula
Siddhartha Joshi
Daher Kaiss
Suraj Kamble
Henrique Kawakami
Sagar Kekare
M V Kiran Kumar
Mounica Kothi
Anand Kumaraswamy
Arun Kurian
Hai Li
Aaron Liou
Chen Liu
Prasanth Mangalagiri
Sam Mirza
Vedprakash Mishra
Kaizad Mistry
Thais Moreira Hamasaki
Praveen Mosalikanti
Hesham Mostafa
Ponnada Naidu
Suriya Natarajan
Odie Ou
Jeff Parkhurst
Anmol Patel
Gary Patton
Chung-Ching Peng
Swaresh Phadke
Pradip Prajapati
Sai Prashant
Disha Puri
Lynn Qian
ARNAB RAHA
Vivek Rajan
Bindu Rao
Erin Rasmussen
Prasenjit Ray
Venkatesh RS
suhas S
Deepmala Sachan
Rocco Salvia
Sandesh Saokar
Deshanand Singh
Ke Sun
Basil Tarabiea
Vivek Tiwari
Zih-Nan Tseng
Divyarajsinh Vaghela
Khris Valencia Chacon
Omer Vikinski
Saripalli Vinay
Alexander Waizman
Hank Wang
Andy Wei
Chris Wilkerson
CH Yang
Ian Young
Farrukh Zafar
Wei Zhou
Session Chairs
Rosario Cammarota
Avani Dave
Daniel Dinu
Priya Iyer
UDAY MALLAPPA
Presentations
Engineering Track Poster
2.5D Design Breakthrough: Unleashing the Power of Automated EMIB Bridges.
Back-End Design
Embedded Systems
Front-End Design
IP
Research Panel
3DIC Design Ecosystem – The Cats That Need Herding!
Design
Engineering Track Poster
A Decade of Evolution in Formal Verification
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
A Methodology to Predict IR Drop Enhancement in BSPDN Compared to FSPDN by Formulating the On-Die IR Drop
Back-End Design
Design
Engineering Tracks
Back-End Design
A Systematic Approach to 3D Cutline Exploration and Benchmarking
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Advancements in Source Synchronous Design Implementation: An EDA Perspective
Back-End Design
Embedded Systems
Front-End Design
IP
DAC Pavilion Panel
Advancing Chip Security to Meet Heightened Requirements
Security
Engineering Track Poster
Automated Floorplan Scaling Solutions and Framework
Back-End Design
Embedded Systems
Front-End Design
IP
Research Manuscript
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision
AI
AI/ML Application and Infrastructure
Research Manuscript
CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis
AI
Design
AI/ML, Digital, and Analog Circuits
Engineering Track Poster
Charting Uncharted Waters: Functional Simulation Reshaping CDC/RDC Constraints Signoff
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Clock parameter tuning with an intelligent adaptive learning to improve performance and power of Multisource Clock Tree Synthesis
Back-End Design
Design
Engineering Tracks
Engineering Track Poster
Coverage-based FV signoff – The complete cleanup methodology
Back-End Design
Embedded Systems
Front-End Design
IP
Tutorial
Deep Dive in Foundry Process Design Kits (PDKs)
EDA
Engineering Track Poster
Design Automation of Minimal Layer Count Microprocessor 2.5D Silicon Interposer
Back-End Design
Embedded Systems
Front-End Design
IP
Research Manuscript
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization
Design
Emerging Models of Computation
Front-End Design
Enhancing Formal Equivalence for Datapath Algorithms: A Proof Strategy with Intermediate Modeling to Address Structural Differences in Implementations
Design
Engineering Tracks
Front-End Design
Work-in-Progress Poster
FastSample: Accelerating Distributed Graph Neural Network Training for Billion-Scale Graphs
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
IP
GPU Power Tracking and Optimization Using Emulation
Engineering Tracks
IP
Research Manuscript
Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems
EDA
Test, Validation and Silicon Lifecycle Management
Work-in-Progress Poster
LEAP: Layout aware Estimation of Analog design Parasitics
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Work-in-Progress Poster
MatHE: A Near-Mat Processing In-Memory Accelerator for Fully Homomorphic Encryption
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security
Engineering Track Poster
Navigating Instruction Length Decode: TAP into IP using three pronged FV Trident
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Physical Design With Intelligence
Back-End Design
Embedded Systems
Front-End Design
IP
Tutorial
Post-Quantum Cryptography: Implementation Attacks and Countermeasures
Security
Research Panel
Power Your Future: Investments for the Chip Design Workforce and Research
EDA
Keynote
Special Event
Systems Foundry - a journey from 'System on a Chip' to 'System of Chips'
Design
IP
Technology and IP Scaling Beyond 5nm
Engineering Tracks
IP
Research Manuscript
Uncovering Software-Based Power Side-Channel Attacks on Apple M1/M2 Systems
Security
Hardware Security: Attack and Defense
IP
Watt's Up with DDR5: Formal Verification Framework for Robust DRAM Power Management
Engineering Tracks
IP
Sessions
Research Manuscript
New Frontiers in Hardware Security
Security
Hardware Security: Attack and Defense
Research Manuscript
What's Your Best Side?
Security
Hardware Security: Attack and Defense
Research Manuscript
On the Right Path: Navigating the Maze of Routing and Clock Tree Synthesis!
EDA
Physical Design and Verification
Research Manuscript
Hardware Security Primitives
Security
Hardware Security: Primitives, Architecture, Design & Test
Research Manuscript
Attacks and Defenses at Microarchitecture Level and Beyond
Security
Hardware Security: Primitives, Architecture, Design & Test