Presentation
Low-Complexity Algorithmic Test Generation for Neuromorphic Chips
DescriptionWe propose an algorithmic test generation method for neuromorphic chips without Design-for-Testability.
Fault activation differentiates a neuron's good output and faulty output.
Fault propagation sensitizes fault effects to differentiate outputs of faulty chips and good chips.
On an L-layer Spiking Neural Network (SNN) model, we achieve 100% fault coverage using O(L) test configurations and test patterns under negligible or no weight variation.
Our results show that test effectiveness is maintained even with 4-bit weight quantization.
We incur no test escape and overkill even under 10% weight variation.
Our total test length is over 73K times shorter than previous works.
Fault activation differentiates a neuron's good output and faulty output.
Fault propagation sensitizes fault effects to differentiate outputs of faulty chips and good chips.
On an L-layer Spiking Neural Network (SNN) model, we achieve 100% fault coverage using O(L) test configurations and test patterns under negligible or no weight variation.
Our results show that test effectiveness is maintained even with 4-bit weight quantization.
We incur no test escape and overkill even under 10% weight variation.
Our total test length is over 73K times shorter than previous works.
Event Type
Research Manuscript
TimeTuesday, June 2511:00am - 11:15am PDT
Location3010, 3rd Floor
EDA
Test, Validation and Silicon Lifecycle Management