Presentation
On Optimization of Robustness of Inter- and Intra-chiplet Interconnection Topology for Multi-chiplet Systems
DescriptionInter- and intra-chiplet interconnection networks play a vital role in the operation of many-core systems made of multiple chiplets. However, these networks are susceptible to faults caused by manufacturing defects and attacks resulting from the malicious insertion of hardware trojans and backdoors. Unlike conventional fault-tolerant or countermeasure methods, this paper focuses on optimizing network robustness to withstand both faults and attacks, while considering constraints of chiplet area and power budget. To achieve this, this paper first defines network robustness as a quantifiable measure based on various network parameters, after which an optimization problem is formulated to optimize the robustness of the network topology. To efficiently solve this problem, an efficient algorithm is proposed. Experimental results demonstrate that proposed method is capable of generating inter- and intra-chiplet interconnection networks that are significantly more robust than existing topology generation method. Specially, proposed method improves robustness over state-of-the-art methods by an average of 14.06% under random faults and by 9.37% under targeted attacks.
Event Type
Work-in-Progress Poster
TimeTuesday, June 256:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security