Presentation
Analysis of 64-bit Parallel Prefix Adders and 32-bit Matrix Multiply Units Designed with 7-nm CNFET
DescriptionIn this paper, we provide the first thorough analysis of 64-bit parallel prefix adders (PPAs) and 32-bit matrix multiply units (MMUs) implemented using 7-nm carbon nanotube field effect transistors (CNFETs). Unlike many previous studies in which researchers performed the analysis of CNFET circuits at the SPICE level, we focus on netlists placed and routed using the state-of-the-art CNFET cell library. This approach enables us to analyze a more complex and wider range of CNFET circuits (i.e., various architectures of parallel prefix adders and matrix multiply units) than researchers in previous studies, while considering various effects of the physical layout of the circuits. Our experimental results show that 7-nm CNFET improves energy-delay products (EDPs) by 90× and 44× on average for PPAs and MMUs, respectively, compared to 7-nm FinFET. In addition, our analysis shows that the impact of wires, particularly on power consumption, is more substantial in CNFET circuits than FinFET circuits, and wire savings are therefore crucial for the optimization of the EDP of CNFET circuits. This study opens up a new opportunity to develop a wire-aware design for CNFET circuits.
Event Type
Work-in-Progress Poster
TimeWednesday, June 265:00pm - 6:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
IP
Security